02-06-2018 02:07 AM - edited 02-17-2018 01:41 PM
I need to design register file that is connected to an ALU in systemverilog, then simulate the top module to verify that operation are performed correctly.
I attached three modules, one for alu, register file, top module, and testbench for top module.
I am having trouble figuring out what to use for the output of the topalu module, since the output of the alu will be fed back to the write data port in register file. Once I figure this out I will figure out the issue with my test bench.
02-14-2018 01:32 AM
This is what you have built, you can see the schematic by opening the elaborated design and hitting F4.
From this you should have an idea of what ports you need in your test bench.
There is no clock in your test bench so nothing will change, you need to include something equivalent to this.
#2.5 clk = 1;
#2.5 clk = 0;
02-17-2018 01:40 PM
I tested the register file separately, so I have four inputs and 2 outputs as shown in the attached txt file.
if I have these conditions,
then the output rd1 and rd2 will be 1, but if I have
rd1 will be 1 and rd2 is dont care 'x'
I got the register file code from my book, but I didn't understand how to use A3 and WD.