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Registered: ‎07-03-2014

Wrong data output from Block RAM using INIT attribute

Hi,

 

I'm simulating a block ram which is directly instantiated in VHDL, not using IP core. This is the instantiation:

 

    HROM_NTSC : RAMB18E1
    -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    -- HROM NTSC
    -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- translate_off
		generic map (
			SIM_DEVICE		=> "7SERIES",
			RAM_MODE			=> "TDP",
			RSTREG_PRIORITY_A	=> "RSTREG",
			RSTREG_PRIORITY_B	=> "RSTREG",
			READ_WIDTH_A 	=> HROM_WIDTH+HROM_P_WIDTH,
			READ_WIDTH_B 	=> HROM_WIDTH+HROM_P_WIDTH,
			WRITE_WIDTH_A 	=> HROM_WIDTH+HROM_P_WIDTH,
			WRITE_WIDTH_B 	=> HROM_WIDTH+HROM_P_WIDTH,
			DOA_REG			=> 0,
			DOB_REG			=> 0,
			WRITE_MODE_A 	=> "READ_FIRST",
			WRITE_MODE_B 	=> "READ_FIRST",
			INIT_A       	=> X"21D67",
			INIT_B       	=> X"21D67",
			SRVAL_A      	=> X"21D67",
			SRVAL_B      	=> X"21D67",
			INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
			INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
			INITP_02 => X"5555555555556000000000000000000000000000000000000000000000000000",
			INITP_03 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA85555555555555555555555",
			INITP_04 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
			INITP_05 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
			INITP_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
			INITP_07 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
			INIT_00 => X"0010000F000E000D000C000B000A000900080007000600050004000300020001",
			INIT_01 => X"0020001F001E001D001C001B001A001900180017001600150014001300120011",
			INIT_02 => X"0430042F042E002D002C002B002A002900280027002600250024002300220021",
			INIT_03 => X"0440043F043E043D043C043B043A043904380437043604350434043304320431",
			INIT_04 => X"0450044F044E044D044C044B044A044904480447044604450444044304420441",
			INIT_05 => X"0860085F085E085D085C085B085A045904580457045604550454045304520451",
			INIT_06 => X"0870086F086E086D086C086B086A086908680867086608650864086308620861",
			INIT_07 => X"0880087F087E087D087C087B087A087908780877087608750874087308720871",
			INIT_08 => X"0C900C8F0C8E0C8D0C8C0C8B0C8A0C890C880887088608850884088308820881",
			INIT_09 => X"0CA00C9F0C9E0C9D0C9C0C9B0C9A0C990C980C970C960C950C940C930C920C91",
			INIT_0A => X"0CB00CAF0CAE0CAD0CAC0CAB0CAA0CA90CA80CA70CA60CA50CA40CA30CA20CA1",
			INIT_0B => X"10C010BF10BE10BD10BC10BB10BA10B910B810B710B610B510B40CB30CB20CB1",
			INIT_0C => X"10D010CF10CE10CD10CC10CB10CA10C910C810C710C610C510C410C310C210C1",
			INIT_0D => X"10E010DF10DE10DD10DC10DB10DA10D910D810D710D610D510D410D310D210D1",
			INIT_0E => X"14F014EF14EE14ED14EC14EB14EA14E914E814E714E614E514E414E314E210E1",
			INIT_0F => X"150014FF14FE14FD14FC14FB14FA14F914F814F714F614F514F414F314F214F1",
			INIT_10 => X"1910190F190E150D150C150B150A150915081507150615051504150315021501",
			INIT_11 => X"1920191F191E191D191C191B191A191919181917191619151914191319121911",
			INIT_12 => X"1930192F192E192D192C192B192A192919281927192619251924192319221921",
			INIT_13 => X"1D401D3F1D3E1D3D1D3C193B193A193919381937193619351934193319321931",
			INIT_14 => X"1D501D4F1D4E1D4D1D4C1D4B1D4A1D491D481D471D461D451D441D431D421D41",
			INIT_15 => X"1D601D5F1D5E1D5D1D5C1D5B1D5A1D591D581D571D561D551D541D531D521D51",
			INIT_16 => X"2570256F256E256D256C256B256A256921681D671D661D651D641D631D621D61",
			INIT_17 => X"2580257F257E257D257C257B257A257925782577257625752574257325722571",
			INIT_18 => X"2590258F258E258D258C258B258A258925882587258625852584258325822581",
			INIT_19 => X"25A0259F259E259D259C259B259A259925982597259625952594259325922591",
			INIT_1A => X"1D671D671D67000029AC25AB25AA25A925A825A725A625A525A425A325A225A1",
			INIT_1B => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_1C => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_1D => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_1E => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_1F => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_20 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_21 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_22 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_23 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_24 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_25 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_26 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_27 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_28 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_29 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2A => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2B => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2C => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2D => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2E => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_2F => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_30 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_31 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_32 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_33 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_34 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_35 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_36 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_37 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_38 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_39 => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3A => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3B => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3C => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3D => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3E => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67",
			INIT_3F => X"1D671D671D671D671D671D671D671D671D671D671D671D671D671D671D671D67"
		)
-- translate_on
		port map(RSTRAMARSTRAM								=> rst_a,
					RSTREGARSTREG								=> '0',
					CLKARDCLK									=> clk_a,
					WEA											=> "00",
					DIADI											=> hrom_zeros,
					DIPADIP										=> hromp_zeros,			
					ENARDEN										=> hen_a,
					ADDRARDADDR(13 downto HSTATE_MSB+1)	=> h_state_zeros,
					ADDRARDADDR(HSTATE_MSB downto 0)		=> h_state_a,			
					DOADO											=> hrom_a,
					DOPADOP										=> hromp_a,
					RSTRAMB										=> rst_b,
					RSTREGB										=> '0',
					CLKBWRCLK									=> clk_b,
					WEBWE											=> "0000",
					DIBDI											=> hrom_zeros,
					DIPBDIP										=> hromp_zeros,
					ENBWREN										=> hen_b,
					ADDRBWRADDR(13 downto HSTATE_MSB+1)	=> h_state_zeros,
					ADDRBWRADDR(HSTATE_MSB downto 0)		=> h_state_b,
					DOBDO											=> hrom_b,
					DOPBDOP										=> hromp_b,
					REGCEAREGCE									=> '1',
					REGCEB										=> '1'  );

 

When simulating, if I read addr $167 (359) I got 0x0017 as data output off the block RAM, when it should be 0x2168, as can be seen in nibble 28 of  INIT_16.

 

What could be happening??

 

Is there any way to convert INIT data into .COE? I want to create the same block RAM using IP core to check if the problem persist.

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