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Adventurer
Adventurer
1,613 Views
Registered: ‎08-04-2018

XADC SIMULATION

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OK, Can anyone kindly provide the exact way to use the SIM_MONITOR_FILE(.txt) input file procedure?

I am frustrated trying to use that method, because clearly that is not working! Or may be I miss it out. 

Please, it's a request. Anyone!

Just please save my soul.

 

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Adventurer
Adventurer
1,728 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe,

 

thank you for your help.

 

Actually, I think it works. Can you let me know if this is right?

 

I just got t! if any one else need some info I think this might work.

 

 

 TIME         VP    VN

xili.PNG

 

 

we need to run the testbench as usual (also can be generated by the tcl command available) .

 

-The important is THE 'VN' AND 'VP' CANNOT BE SEEN WORKING IN THE SIMULATION PART(for me it was "U").  the source is from the community forum, someone had posted this, thanks to them

 

-don't get confused with TIME and the XADC dclk_in in the block diagram (see below for more)

since I use DRP interface, I continued exrtacting data using the timing sequence (i.e reading data from the registers after drdy signal goes high)

- though you dont see the VP and VN signal changin, from the file the values will be actually read and converted and stored in the registers, as it does normally. 

 

 my block design 

xili.PNG

testbench:

 

xili.PNG

 

i just read the data_i values and send it to voltage_o

 

for my part, the values are mentioned in the above figure, and the output from the simulation can be seen here. 

 

xili.PNG

 

xili.PNG

 

The convertion is not exact because my values are random and the adc converstion time is not considered. Due to that may be the values are not seen very accurately. Or is this wrong? its not right what I have here?

 

kindly let me know, thanks in advance.

 

26 Replies
Scholar drjohnsmith
Scholar
1,572 Views
Registered: ‎07-09-2009

Re: XADC SIMULATION

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I dont know

 

but the key is where you put the file in the folder structure,

 

there have been MANY comments on this in the forums

 

but it seems that unless you are using a script, its not streight forward,

 

Im hoping some one will come up with a definitive answer.

 

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Xilinx Employee
Xilinx Employee
1,560 Views
Registered: ‎05-22-2018

Re: XADC SIMULATION

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Adventurer
Adventurer
1,526 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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OK, Can anyone atleast guide me as to how do I provide the value example VP = 0.9 to vn_in in the test bench? how do i convert? 

 

 

Thank you

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Xilinx Employee
Xilinx Employee
1,509 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

As I described in your another post "Simulation-data type":

For this case, the input pin of vp_in and vn_in is for analog signals in hardware. And in testbench, analogy signals can't be fed to vp_in directly. In port declaration of xadc, the type of vp_in is 'std_logic', it can't be fed by analogy signal.

For simulation of XADC, analog signals are read from a file by the simulation model. The SIM_MONITOR_FILE attribute used in the XADC instantiation points the model to the location of this file known as the Analog Stimulus file. You can find the description of this situation in ug480.

BR,

Martin

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Adventurer
Adventurer
1,501 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe,

 

Yes, I have placed the file in the exact location, the design.txt is in the default location, to cross check this I deliberately made cahges(removed the 'TIME' stamp) and ran the simulation, I saw that the wave form had no signals whatsoever, but again after inserting it back, I see the waveform as 'U' as shown below. But I don't understand why no input then? 

 

xili.PNG

 

kindly help me. Thank in advance.

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Xilinx Employee
Xilinx Employee
1,497 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

Don't observe vp_in and vn_in, they are already been forced to constant values in testbench.

You can observe signal of '/xadc_wiz_0_tb/Analog_Wave_Vp_Vn' as following:

Capture.PNG

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Xilinx Employee
Xilinx Employee
1,495 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka

A reminder is that you need to choose Analog format for 'Analog_Wave_Vp_Vn' as following picture to show analog value:

Untitled.png

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Adventurer
Adventurer
1,489 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe,

 

 

Can I ask you how did you provide that 'Analog_Wave_Vp_Vn' in your design? why is that 12 bits there? how are you feeding the value for that? For me to change waveform to analog type, the waveform should first take inputs that I feed..

 

Thanks in advance 

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Xilinx Employee
Xilinx Employee
1,473 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

This 12bits signal exists in testbench of the example design. The simulate module of XADC read data from stimuli file and output analog value to this signal and you can observe it in wave form. For the stimuli file, it can be defined when you configure this IP.

Capture.PNG

It is easy to reproduce my simulation wave form by example design. If you can't reproduce it, I can send you the example design from my side.

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Adventurer
Adventurer
1,551 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe,

 

yes, the file is located i the default location, hence I changed the values in th edefault location .txt file and tried simulation. But I request you to kindly send a example design in vhdl method, please.

 

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
1,544 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

Please tell me the version of Vivado from your side. I will try to generate the example design with the same Vivado version from your side.

BR,

Martin

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Adventurer
Adventurer
1,537 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe

 

I am using the 2016.4 verion.

 

Thanks a lot.

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Xilinx Employee
Xilinx Employee
1,510 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

The zip file size is too big to upload. Could you leave your email address here for me to send it to you by EZmove?

 

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Adventurer
Adventurer
1,505 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi @martinwe

 

its anythingtoclash@gmail.com

 

thanks in advance.

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Xilinx Employee
Xilinx Employee
1,497 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

I send it out by EZmove.  Only verilog testbench can be generated for this IP.

And you can get detailed information from these two documents: pg091, ug480.

BR,

Martin

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Highlighted
Adventurer
Adventurer
1,729 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

Jump to solution

Hi @martinwe,

 

thank you for your help.

 

Actually, I think it works. Can you let me know if this is right?

 

I just got t! if any one else need some info I think this might work.

 

 

 TIME         VP    VN

xili.PNG

 

 

we need to run the testbench as usual (also can be generated by the tcl command available) .

 

-The important is THE 'VN' AND 'VP' CANNOT BE SEEN WORKING IN THE SIMULATION PART(for me it was "U").  the source is from the community forum, someone had posted this, thanks to them

 

-don't get confused with TIME and the XADC dclk_in in the block diagram (see below for more)

since I use DRP interface, I continued exrtacting data using the timing sequence (i.e reading data from the registers after drdy signal goes high)

- though you dont see the VP and VN signal changin, from the file the values will be actually read and converted and stored in the registers, as it does normally. 

 

 my block design 

xili.PNG

testbench:

 

xili.PNG

 

i just read the data_i values and send it to voltage_o

 

for my part, the values are mentioned in the above figure, and the output from the simulation can be seen here. 

 

xili.PNG

 

xili.PNG

 

The convertion is not exact because my values are random and the adc converstion time is not considered. Due to that may be the values are not seen very accurately. Or is this wrong? its not right what I have here?

 

kindly let me know, thanks in advance.

 

Xilinx Employee
Xilinx Employee
1,483 Views
Registered: ‎09-24-2017

Re: XADC SIMULATION

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Hi @benaka,

A good way to confirm your result is to feed easy observed stimuli data to your simulation, for example sin data value. And then you can judge it by boserving sin wave.

 

 

 

 

Adventurer
Adventurer
1,475 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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yup, it works. 

 

Thank you :) 

Visitor lich915
Visitor
341 Views
Registered: ‎03-27-2019

Re: XADC SIMULATION

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HI!@martinwe

 

The same question occurs to me.

I tried to feed XADC by using the 'analog sim option, however, it doesn't work.

Can you send me the zip file? my version is 2018.2.

E-mail:1482650147@qq.com.

QQ截图20190412140834.png
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Adventurer
Adventurer
333 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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your "Sim file location", do you have the file path added correctly or the correvct format and values in the default file/path?
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Visitor lich915
Visitor
325 Views
Registered: ‎03-27-2019

Re: XADC SIMULATION

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yeah! 

I referred to the users guide.It's no problem.

The data it output is 16bit, I wonder how to make it a 12-bit sin wave?

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Adventurer
Adventurer
319 Views
Registered: ‎08-04-2018

Re: XADC SIMULATION

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Hi, 

You only need to consider 12-bits not all 16. There 4 bits which are indicating the settling time and some other functionality. So, the MSB 12-bits  are the actual values, ignore the other 4 bits.

 

Accept/Kudo the solution in case you have your answer so it can help others.

 

 

Thanks.

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Scholar drjohnsmith
Scholar
308 Views
Registered: ‎07-09-2009

Re: XADC SIMULATION

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If I remember, the 12 bits data from the adc is stuffed into the top 12 bits of the 16 bit output,

sin_out <= xadc_value( 15 downto 0);

where xadc_value is the 16 bits that you get from the adc.
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Visitor lich915
Visitor
295 Views
Registered: ‎03-27-2019

Re: XADC SIMULATION

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Hi,

Thanks for your reply, I realized the 12bit. 

I meet another problem. I code the sim file in specific folder, while after running the simulation, the design.txt I've codded before was reset.

what could result in that?

 

1.png
2.png
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Scholar drjohnsmith
Scholar
284 Views
Registered: ‎07-09-2009

Re: XADC SIMULATION

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its normal to start a new thread for a new problem, ....
could it be that you put the txt file in a the sim folder thats re created new on each sim run .
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Visitor lich915
Visitor
257 Views
Registered: ‎03-27-2019

Re: XADC SIMULATION

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I got it.
Only the example sim file can be located in the suggested folder, I put my .txt in any other folder, then it make sense.

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