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Adventurer
Adventurer
1,234 Views
Registered: ‎08-04-2018

XADC proper simulation

Hi guys, 

 

 

From a while I am trying to find a way to simulate the xadc and i have not found a proper way and hence I tried again and here is the status

 

 

xili.PNG

here is my block diagram, here is my project manager pic

xili.PNG

 

here is my design_1_wrapper.vhd

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
dclk_in => dclk_in,
vn_in => vn_in,
vp_in => vp_in
);
end STRUCTURE;

 

 

and here is my testbench 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.


library UNISIM;
use UNISIM.VComponents.all;

 

 

entity XADC_test_tb is
-- Port ( );
end XADC_test_tb;

 

architecture Behavioral of XADC_test_tb is

component design_1_xadc_wiz_0_0
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC);
end component;
signal eoc : STD_LOGIC ;
constant clk_period : time := 0.1ns;

 

begin
uut: design_1_xadc_0_0 port map(
dclk_in => dclk_in,
vp_in => vp_in,
vn_in => vn_in
);


clk: process
begin
dclk_in <= '0';
wait for clk_period/2;
dclk_in <= '1';
wait for clk_period/2;


end process;
end Behavioral;

 

here is my log 

 

INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity XADC_test_tb
ERROR: [VRFC 10-91] design_1_xadc_0_0 is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:51]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:58]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:60]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:38]
INFO: [VRFC 10-240] VHDL file E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

 

 

please someone help me out here. I have various permutation combination to try declare the not declared and I fail every time.

 

what am i doing wrong here?

 

 

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7 Replies
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Xilinx Employee
Xilinx Employee
1,202 Views
Registered: ‎09-24-2017

Hi @benaka

In your testbench, you declare component of design_1_xadc_wiz_0_0, but you instantiate component with name of design_1_xadc_0_0 in your testbench. Their name should be the same.

 

You can instantiate your wrapper module, design_1_wrapper in your testbench, like this:

...

component design_1_wrapper

port(...)

end component;

...

begin
uut: design_1_wrapper port map(.....);

......

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Highlighted
Adventurer
Adventurer
1,190 Views
Registered: ‎08-04-2018

Hi @martinwe

 

I made a few changes in the tb as u mentioned and here it is

1)

 

xili.PNG

 

2) Generated wrapper 

 

xili.PNG

 

3) the project window 

 

xili.PNG

 

As seen i till see the uut in missing sources indication. 

 

4) and the tcl console shows me error 

 

xili.PNG

I still am not sure where am I going wrong.

 

thanks in advance.

 

 

 

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Highlighted
Xilinx Employee
Xilinx Employee
1,186 Views
Registered: ‎09-24-2017

dck_in, vp_in and vn_in should be declared in testbench:

signal dclk_in, vp_in, vn_in : std_logic;

 

 

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Highlighted
Adventurer
Adventurer
1,182 Views
Registered: ‎08-04-2018

Yes, I just found out the same, I came to answer it here and see you already mentioned. 

But It still doesnt help in simulation of the signals with the .txt file but. 

 

here is the simulation result picxili.PNG

 

and the test file data here, 

xili.PNG

 

the project manager window here,

xili.PNG

 when I run the simulation , the xadc still doesn't take the values. 

 

what am I doing wrong? or why is this happening?

 

 

Thanks in advance.

 

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Highlighted
Xilinx Employee
Xilinx Employee
1,168 Views
Registered: ‎09-24-2017

For simulation of XADC, analog signals are read from a file by the simulation model. The SIM_MONITOR_FILE attribute used in the XADC instantiation points the model to the location of this file known as the Analog Stimulus file. You can find the description of this situation in ug480.

 

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Adventurer
Adventurer
1,158 Views
Registered: ‎08-04-2018

Hi @martinwe,

 

Here is my test bench 

https://forums.xilinx.com/t5/Simulation-and-Verification/XADC-proper-simulation/m-p/893370/highlight/true#M23601

 

 I am not sure what do you mean by driving the signal, the data for these pins are supposed to be taken from that .txt file right?

Or can you please show me how to drive the signals that you mean.

 

 

Thanks in advance.

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Highlighted
Xilinx Employee
Xilinx Employee
1,141 Views
Registered: ‎09-24-2017

For the topic of stimuli file for XADC_wiz, refer to another post:

https://forums.xilinx.com/t5/Simulation-and-Verification/XADC-SIMULATION/m-p/897078#M23758

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