In attempting to get simple Verilog code which utilizes an XPM_FIFO macro to simulate using Vivado 2017.4, the following lines were displayed in the TCL Console (including similar redundant lines, and other INFO lines, etc.):
Warning: Vivado Simulator does not currently support the SystemVerilog Assertion syntax used within XPM_CDC. Messages related to potential misuse will not be reported.
Error: [XPM_FIFO 1-6] CDC_DEST_SYNC_FF (8) value is specified for this configuration, but CDC_DEST_SYNC_FF value can not be modified from default value when RELATED_CLOCKS parameter is set.
WARNING: [Simulator 45-29] Cannot open source file /wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv: file does not exist.
The Error is self-explanatory, but not anticipated per UG974 (v2017.4) p.42, at least if the CDC_SYNC_STAGES attribute (which was specified as 8) is being complained about.
With XPM fifo being fairly new and I bet Xilinx engineers dont use Vivado Simulator (they probably use a full featured one with SVA abilities, hence the warning) they probably didnt notice all this stuff falling out of their own simulator.
I have a similar problem, only that I dont have an SVA licence for my external simulator, so currently there is no way for me to simulate the XPM FIFO, which is very annoying (I have to fall back to the very annoying FIFO generator):