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Adventurer
Adventurer
2,878 Views
Registered: ‎12-20-2010

XSIM 43-3241 error: gthe4_channel_002.vp Node SIM_VERSION is not annotated

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Xsim generates the following error during elaboration of my design.   The design contains a Chip2Chip bridge using GTH transceivers.   The simulation testbench is written in System Verilog.

 

ERROR: [XSIM 43-3241] File /wrk/2017.1/nightly/2017_04_14_1846317/data/secureip/gthe4_channel/gthe4_channel_002.vp, Line Num 22892, Node SIM_VERSION is not annotated.

 

 

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Adventurer
Adventurer
4,921 Views
Registered: ‎12-20-2010

Re: XSIM 43-3241 error: gthe4_channel_002.vp Node SIM_VERSION is not annotated

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After opening a support ticket, I was told this is a known bug and will be fixed in 2017.3.

 

There is a work-around.  The error only occurs during mixed-mode simulations.  Set the target language to Verilog and regenerate all the outputs so there are no VHDL source files, and then simulation should run.

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Xilinx Employee
Xilinx Employee
2,839 Views
Registered: ‎10-24-2013

Re: XSIM 43-3241 error: gthe4_channel_002.vp Node SIM_VERSION is not annotated

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Hi @kinkeads

 

Please check if the following AR is applicable to you.

https://www.xilinx.com/support/answers/63972.html

Thanks,Vijay
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Adventurer
Adventurer
2,822 Views
Registered: ‎12-20-2010

Re: XSIM 43-3241 error: gthe4_channel_002.vp Node SIM_VERSION is not annotated

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AR 63972 recommends overriding the SIM_VERSION parameter value, but I do not see this property on any devices in my IP Integrator block design.

 

Is SIM_VERSION a property attached to an IP block?  I would expect it to be on the AURORA_64B66B IP block since it contains the GT transceivers.

Thanks!

 

 

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Adventurer
Adventurer
4,922 Views
Registered: ‎12-20-2010

Re: XSIM 43-3241 error: gthe4_channel_002.vp Node SIM_VERSION is not annotated

Jump to solution

After opening a support ticket, I was told this is a known bug and will be fixed in 2017.3.

 

There is a work-around.  The error only occurs during mixed-mode simulations.  Set the target language to Verilog and regenerate all the outputs so there are no VHDL source files, and then simulation should run.

0 Kudos