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Visitor
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Registered: ‎02-12-2014

[XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. (Vivado 2014.1)

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Hello,

 

I was going to request help on this issue, but found a workaround. However, I would still appreciate input on the cause of this problem.

 

On my 64-bit Win7 machine, Vivado 2014.1 fails launching simulation with the message "ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received."

 

I managed to track this behavior down to a single line in the following:

 

-- this triggers the error:  
procedure move_line( variable source : inout line; variable dest : inout line; constant movelength : in natural := C_LOG_LINEWIDTH; constant splitchar : in string := " " -- empty means move on length ) is variable v_part1_end : natural := 0; variable v_part2_start : natural := 0; variable v_sourcestring : string(1 to source'length) := source.all; variable v_copystring : string(1 to movelength); begin --...

 

-- this does not trigger the error:  
procedure move_line( variable source : inout line; variable dest : inout line; constant movelength : in natural := C_LOG_LINEWIDTH; constant splitchar : in string := " " -- empty means move on length ) is variable v_part1_end : natural := 0; variable v_part2_start : natural := 0; variable v_sourcestring : string(1 to source'length);-- := source.all; variable v_copystring : string(1 to movelength); begin v_sourcestring := source.all;
--...

That is, assigning the variable in the procedure preamble triggers the error, while assigning it in the body does not. Any thoughts appreciated!

 

On another machine, 32-bit Win7, the error does not happen. Instead the simulation is launched successfully, but fails at a specific point in the code (not coinciding with the code excerpt above) with the message "ERROR: Attempting to dereference a null access value". I have not investigated this error.

 

The code worked fine in Vivado 2013.4.

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Moderator
Moderator
29,767 Views
Registered: ‎01-16-2013

Hello @asmundr ,

 

I have tried your test case. I am also able to reproduce issue it with win 7- 64 bit.

I have tried same using RHEL (Linux) and its working fine.

I have also tried with 2013.4 in both OS i.e. Win & Linux its working fine for me.

 

As you mentioned you can use Linux or you can use your workaround for now and proceed further.

I will keep you posted for further info regarding this.

 

Thanks,

Yash

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Moderator
Moderator
20,673 Views
Registered: ‎01-16-2013
Hello,

Could you please send me the test case?
I will try at my end and let you know the feedback.

Thanks,
Yash
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Visitor
Visitor
20,657 Views
Registered: ‎02-12-2014

This is all it takes to trigger the error:

library ieee;
use std.textio.all;

entity sim_error_tb is
end sim_error_tb;

architecture beh of sim_error_tb is
    
  procedure foo_procedure(
    variable foo_var_line : inout line
    ) is
    variable foo_var_string : string(1 to foo_var_line'length) := foo_var_line.all;
  begin
    -- procedure does nothing
  end procedure;
    
begin
  p_main : process is
    variable foo_var_line : line;
  begin  
    foo_procedure(foo_var_line);
    wait;
  end process p_main;
end architecture beh;

 Gives log output:

Vivado Simulator 2014.1
Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2014.1/bin/unwrapped/win64.o/xelab.exe --debug typical --relax -L xil_defaultlib -L secureip --snapshot sim_error_tb_behav --prj D:/sim_error_project/sim_error_project.sim/sim_1/behav/sim_error_tb.prj xil_defaultlib.sim_error_tb 
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-165] Analyzing Verilog file "C:/Xilinx/Vivado/2014.1/data/verilog/src/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-163] Analyzing VHDL file "D:/sim_error_project/sim_error_tb.vhd" into library xil_defaultlib
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling architecture beh of entity xil_defaultlib.sim_error_tb
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

(With this example and my above proposed workaround, "ERROR: Attempting to dereference a null access value" is triggered. The same thing happens in Vivado 2013.4, with or without the workaround. This is not a problem.)

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Contributor
Contributor
20,600 Views
Registered: ‎11-21-2013

I am having the same issue on multiple machines (Win7 64-bit).  Revert back to 2013.4 and it works.

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Moderator
Moderator
29,768 Views
Registered: ‎01-16-2013

Hello @asmundr ,

 

I have tried your test case. I am also able to reproduce issue it with win 7- 64 bit.

I have tried same using RHEL (Linux) and its working fine.

I have also tried with 2013.4 in both OS i.e. Win & Linux its working fine for me.

 

As you mentioned you can use Linux or you can use your workaround for now and proceed further.

I will keep you posted for further info regarding this.

 

Thanks,

Yash

View solution in original post

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Moderator
Moderator
20,542 Views
Registered: ‎01-16-2013
Hello @asmundr ,

Its under consideration.
Please close this thread if you don't have any concerns for now.

Thanks,
Yash
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Visitor
Visitor
20,310 Views
Registered: ‎02-12-2014

FYI: this issue is still present in Vivado 2014.2.

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Explorer
Explorer
19,971 Views
Registered: ‎12-06-2013

Spent two days tracking this down.....please fix this.

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Moderator
Moderator
19,959 Views
Registered: ‎04-17-2011

@jeff_king Please create a new thread if your code description doesnt match the one discussed here. These issues are OS/code specific.

Regards,
Debraj
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Explorer
Explorer
19,957 Views
Registered: ‎12-06-2013

@debrajr I have the same issue, Win 7 64 & 32 bit, 2014.2

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Visitor
Visitor
10,400 Views
Registered: ‎05-19-2008

I am having this issue on Vivaod 20414.4 64-bit Win 7. I don't have access to change the code because it was delivered by a vendor.

 

I had the same issue with synth and I had to tun off cross boundary optimization.

 

when will this be fixed?

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Scholar
Scholar
10,322 Views
Registered: ‎04-04-2014

Just to be clear, as I am now having this problem. What exactly will cause the bug?

 

The error occurs when declaring and assigning a variable in a procedure preamble? But not when assigning it in the body? I know this was the case in the example that started this thread but is it more general? 

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Scholar
Scholar
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Registered: ‎04-04-2014

Ok, afte a few hours I have located the offended line in my code. It is as follows:

 

constant DEF_LEDS_OUT: std_logic_vector(3 downto 0) := leds_string_to_vec(DEF_LED1, DEF_LED2);

 

- DEF_LED1 and DEF_LED2 are generics of type string, passed to the module containing the above line.

- leds_string_to_vec is a procedure that converts these two strings into a 4 bit vector.

 

So, I have changed the generics so that I have a single generic called DEF_LEDS_OUT. then in the module that instatiaes this one, I have used the procedure there instead.

 

generic map(

 

    DEF_LEDS_OUT => leds_string_to_vec(DEF_LED1, DEF_LED2);

 

)

 

So, not exactly the same as the thread example, but close. No clues in the xelab.log file as to where the problem was. Plus, I assign signals and constants in these places all over my project. Maybe the differenc eis that this called a procedure in doing so.

 

Thought this might be useful for anyone else who is time-wasting in a similar way...

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Visitor
Visitor
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Registered: ‎03-20-2018

I have an AXI4 Full based module that implements components from the XMP   "Xilinx Parameterized Macros" library.

You might have a simple error (which is easy to do after trying to route a hundred or so signals between instances, packages, declarations, and procedures) its easy to overlook something. In this case, overlooking a signal port assignment directly to a type, will throw this exception. 

 

MyLabel : someXMPLibraryInstance

   generic map(

      magicNumber := 3

   ) 

  port map(

  myclock  => globalClock, 

  myReset => globalReset, 

  myMistake => std_logic, --mistake is here!

  dataSig    => Din,

  dataOut  => Dout

  );

 

I've tested this in 2018.2 (but not extensively at all) I need to push forward on a project.

 

Anyway, how this helps someone else.

 

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

 

 

 

vhdlerror.png
vhdlFix.png
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