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Observer
Observer
1,186 Views
Registered: ‎11-13-2017

[XSIM 43-3316] Signal SIGSEGV received. during elab

Hi 

 

I am getting a segmentation fault during elab command. My command looks like 

 

xvlog --sv -f filelist.f

 

My filelist has a mix of verilog and system verilog files (a dummy filelist.f is as follows)

 

verilog_file1.v

verilog_file2.v

sv_file2.sv

 

... the stack trace with the error message is as follows 

 

[0] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4e89be]
[1] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x502693]
[2] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x50226b]
[3] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x503ced]
[4] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[5] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[6] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[7] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[8] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[9] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[10] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[11] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[12] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[13] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[14] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[15] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[16] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[17] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[18] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[19] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[20] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[21] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[22] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[23] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[24] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[25] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[26] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[27] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[28] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[29] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[30] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[31] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[32] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[33] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[34] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[35] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[36] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4ea85d]
[37] /opt/Xilinx/Vivado/2017.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f01b95883a6]
[38] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4f9af0]
[39] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4e6071]
[40] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4813a4]
[41] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4677c2]
[42] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x4760c6]
[43] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x44b9ff]
[44] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0) [0x7f01b7aa0830]
[45] /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab() [0x465631]

 

Can someone please help with this issue?

 

Thanks

 

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3 Replies
Highlighted
Moderator
Moderator
1,173 Views
Registered: ‎02-07-2008

Re: [XSIM 43-3316] Signal SIGSEGV received. during elab

@gaurav_ag, does the issue also occur in 2017.3?

 

Can you submit a test case, enabling for the issue to be investigated locally?

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Xilinx Employee
Xilinx Employee
1,164 Views
Registered: ‎08-01-2008

Re: [XSIM 43-3316] Signal SIGSEGV received. during elab

check these ARs
https://www.xilinx.com/support/answers/69251.html
https://www.xilinx.com/support/answers/64809.html
Thanks and Regards
Balkrishan
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Moderator
Moderator
1,147 Views
Registered: ‎04-24-2013

Re: [XSIM 43-3316] Signal SIGSEGV received. during elab

Hi @gaurav_ag,

 

If you are using SystemVerilog then check out User Guide 900 (attached) for which features are supported in Simulation.

This may help identify what is causing the elab error.

 

Best Regards
Aidan

 

 

 

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