hi
I want to simulate a verilog file and a test bench by vivado, but get below error. the Log tab is copied below:
Vivado Simulator 2013.3
Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2013.3/bin/unwrapped/win64.o/xelab.exe --debug typical --relax --mt off -L work -L unisims_ver -L unimacro_ver -L secureip --snapshot test_bench_behav --prj C:/Users/Lenovo/Desktop/RR/project_1/project_1.sim/sim_1/behav/test_bench.prj work.test_bench work.glbl
Turned off multi-threading.
Determining compilation order of HDL files.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running fuse with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
INFO: [VRFC 10-165] Analyzing Verilog file "C:/Users/Lenovo/Desktop/RR/project_1/project_1.srcs/sources_1/imports/imports/multiplier.v" into library work
INFO: [VRFC 10-165] Analyzing Verilog file "C:/Users/Lenovo/Desktop/RR/project_1/project_1.srcs/sources_1/imports/imports/test_bench.v" into library work
INFO: [VRFC 10-165] Analyzing Verilog file "C:/Xilinx/Vivado/2013.3/data/verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.multiplier
Compiling module work.test_bench
Compiling module work.glbl
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/test_bench_behav/obj/xsim_0.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
I use vivado 2013.03, also use ISE14.02 but unfortunately get similar error.
what can I do to solve this problem.
