02-07-2020 01:12 AM
I'm developing a core where arrays of STD_LOGIC_VECTOR are used.
Some SLV signals have parametric width, so when width=0 these arrays are composed of N elements of SLV(-1 downto 0).
When I try to simulate the core with XSIM, all works fine until I try to add these signals to the waveform window.
On the picture above, if I drag and drop one of the arrays from left to right, XSIM and Vivado crashes and closes.
It seems there's a problem with null SLV, probably ranges are not checked on visualization.
How can I fix this?
02-07-2020 02:38 AM
02-07-2020 02:59 AM - edited 02-07-2020 03:09 AM
a (-1 downto 0) array is a valid array size - a null (0 length) array. When you parameterise blocks with a width paramter (for example) you can set the WIDTH to 0 and if your declaration is
data : in std_logic_vector(WIDTH-1 downto 0);
Then (-1 downto 0) will result when WIDTH is set to 0 (ie. you want the interface removed).
As a side note, (-1 to 0) would be an illegal range for a std_logic_vector as slv is declared as having a natural range, where the smallest legal index is 0 (this is also the same for signed/unsigned). This is unless the range is a null range, when such indeces are allowed. The fixed_pkg allows -ve indeces to indicate the power of two the bit represents.
Xsim is not alone in crashing with null signals on the waveform. ActiveHDL also did this until a couple years ago.
Also note, Synthesis also has problems with null arrays inside records
edit: This appears to finally be fixed in 2019.2! :)
02-07-2020 03:18 AM - edited 02-07-2020 03:20 AM
thanks for noticing me about it.
I encountered indeed a similar problem with records a couple of weeks ago, where again -1:0 ranges have problems.
Maybe it has been fixed in 2019.2 as well... maybe it worths a try...
Anyway: Xilinx SHALL invest some time to fix these basic issues!!