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315 Views
Registered: ‎08-14-2019

XSim errors while starting behavioral simulation

Xsim (Vivado 2019.1) generates the following error during behavioral simulation of my design. The design contains a 10G ethernet IP using GTH transceivers. The design contains both verilog and vhdl files.

ERROR: [XSIM 43-3241] File /wrk/2019.1/continuous/2019_05_24_2552052/data/secureip/gthe4_channel/gthe4_channel_002.vp, Line Num 22720, Node SIM_VERSION is not annotated.
ERROR: [XSIM 43-4542] Design has hierarchical references, for which we have limited support in mixed language scenarios. You may try to compile using the "-dup_entity_as_module" option for the xelab command.

How to work around those errors?

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3 Replies
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Scholar
Scholar
307 Views
Registered: ‎08-07-2014

Re: XSim errors while starting behavioral simulation

anusua.das9@gmail.com,

Is this the 10G Ethernet MAC v15.1 IP core from Xilinx?

If so, the PG072 June 6, 2018 docu has an example_design with this core? Did run a simulation of this example_design to test the IP core before using it in your own design?

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301 Views
Registered: ‎08-14-2019

Re: XSim errors while starting behavioral simulation

Hi,

It is 10G/25G Ethernet Subsystem (3.0) from Xilinx. I have already built an example design for this, and the simulation runs perfectly fine with the example design.

FPGA used: Zynq Ultrascale+

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Adventurer
Adventurer
155 Views
Registered: ‎12-20-2010

Re: XSim errors while starting behavioral simulation

I'm getting the same error message.  Were you able to find a fix?

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