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Visitor
Visitor
3,841 Views
Registered: ‎07-09-2013

Xilinx DCM Post-Route Simulation Problem

I am attempting to perform a post-route simulation on a design containing a Xilinx DCM on a Virtex-II Pro used in Variable Phase Shift mode.

 

In behavioral simulation, when the DCM first locks and no phase shift is applied, the reference clock (clkin) and the clk0 (clkfb) of the DCM are in phase.

 

However, in the post-route simulation, when the DCM first locks and no phase shift is applied, the reference clock and the clk0 (clkfb) of the DCM are not at all in-phase.

 

I am resetting the DCM and applying phase shift exactly according to the spec sheet and Xilinx App Notes, and everything works as expected in behavioral simulation. Is this a known limitation of the Xilinx post-route DCM model, or does this reflect actual behavior? If it does reflect actual behavior, then how do I start the design with 0 phase shift between the reference clk (clkin) and clk0/clkfb such that it works in post-route simulation? 

 

Thanks in advance for any help you can provide.

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Moderator
Moderator
3,831 Views
Registered: ‎04-17-2011

Post PAR simulation would take into account the component delay of DCM, so the output clock would be slightly shifted from the input. This value would be evident if you see the Timing Report and look for the path which passes through the DCM (CLKIN to CLK0). Also, see if the CLKFBIN is connected.

You may also paste your code snippet highlighting the DCM instance for others to comment.
Regards,
Debraj
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Visitor
Visitor
3,816 Views
Registered: ‎07-09-2013

Hi debrajr,

 

Thanks for your response. I have a more general question before I post my DCM code. I am using the Variable Phase Shift feature on the DCM in the Virtex-II Pro. DCM documentation states that, in this mode, you can adjust the phase shift between

1. CLKIN

and

2. CLKFB/CLK0, CLK90, etc.

 

However, how do I ensure I start with 0 phase shift between CLKIN and CLK0 before I begin shifting the phase with variable phase shift?

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Moderator
Moderator
3,775 Views
Registered: ‎10-04-2011

Hello,

 

The feedback path is what performs the automatic alignment to the incoming clock. This feedback path contains a path that is simular to what your logic will contain - that is a buffer and routing that is similar to the majority of REGs on the clock tree. This way any dynamic changes in operating conditions will be acounted for, and this feedback input is what the DCM samples to maintain alignment. However, the input path is a fixed path, and so the DCM contains a fixed shift value meant to remove the delay. Because this fixed path delay may vary based on placement, the phase alignment between input and output clocks of the DCM will not be 100% aligned. But really all that matters here is capturing your input data in reference to the external clock. As long as you center the clock with the DCM (equal setup and hold slack) across the incoming data, you will ensure maximum operation speed and reliability.  

 

So, to ensure phase alignment with small variations as noted, simply connect the feedback path with buffer. Use the variable phase shift to further align your clock for maximum input slack. Same applies to output phase adjust though most people use a separate DCM for that to separate that phase adjustment from the input. 

 

OK, hope this helps a bit ...

 

Scott

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