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Explorer
Explorer
10,263 Views
Registered: ‎08-23-2011

Xilinx GTX logicore IP simulation in VCS

hi,

 

i was trying to simulate the Xilinx GTX logicore IP (in PCIe mode) in vcs, using the sample design testbench provided by xilinx. xilinx docs/user manuals recommend the following simulation tools -

• ISE Simulator (ISim) software 13.4
• Mentor Graphics ModelSim 6.6d
• Cadence Incisive Enterprise Simulator (IES) 10.2
• Synopsys Verilog Compiler Simulator (VCS) and VCS MX E-2011.03

 

i was able to simulate the sample design in ISim and VCS MX E-2011.03 successfully.

 

however when i changed the vcs version to a different verion - vcs MX vF-2011.12 or vcs MX 2013, i got the following error - 

Error-[VLOG_DBSE] DB file size check error
Size of db file 'dve_filename.db' in verilog logical library in directory
'/home/kumarz/vcs_mx_vF2011_libs/virtex6/verilog/secureip/AN.DB' has been
changed (compared with the record of it's last dumping), the library should
have been corrupted. Please remove all db files in that directory and re-analyze the library.

 

I wanted to know if

1)the sample design provided by xilinx for GTX core can ONLY be simulated on vcs mx E 2011.03 and no other version of vcs? is this a xilinx sample design testbench limitation?

2)Can the GTX core itself (used in my own custom design, with my own TB etc.) be simulated on some other version of vcs?

3)is there a way to work around the Error-[VLOG_DBSE]?

 

please let me know, thanks in advance for your inputs ...

 

z.

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4 Replies
Xilinx Employee
Xilinx Employee
10,254 Views
Registered: ‎10-24-2013

Re: Xilinx GTX logicore IP simulation in VCS

Hi,

Please dont post duplicate posts.
http://forums.xilinx.com/t5/General-Technical-Discussion/Xilinx-GTX-Logicore-sim-in-VCS/m-p/558674
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
10,241 Views
Registered: ‎07-16-2008

Re: Xilinx GTX logicore IP simulation in VCS

Did you re-compile the simulation libraries after changing the VCS version?

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Explorer
Explorer
10,222 Views
Registered: ‎08-23-2011

Re: Xilinx GTX logicore IP simulation in VCS

hi,

 

yes. i did recompile the vcs libs for a newer vcs version. however i keep getting the error i had mentioned - 

 

Error-[VLOG_DBSE] DB file size check error
Size of db file 'dve_filename.db' in verilog logical library in directory ...

 

is this  a limitation because i am using xilinx sample design TB or is this a limitation of the  GTX wrapper itself?

 

is the Xilinx GTX wrapper simulatable in ... say vcs MX 2013 ... (using our custom design/TB)? 

 

please let me know ...

 

z.

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Xilinx Employee
Xilinx Employee
10,181 Views
Registered: ‎07-16-2008

Re: Xilinx GTX logicore IP simulation in VCS

From the error message, it looks the old compiled library is still referenced.

Error-[VLOG_DBSE] DB file size check error
Size of db file 'dve_filename.db' in verilog logical library in directory
'/home/kumarz/vcs_mx_vF2011_libs/virtex6/verilog/secureip/AN.DB' has been
changed (compared with the record of it's last dumping), the library should
have been corrupted. Please remove all db files in that directory and re-analyze the library.

 

Please ensure the correct synopsys_sim.setup is used for the new simulation.

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