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amahpour
Observer
Observer
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Registered: ‎01-28-2015

Xilinx IP Path Generation in Questa Compile.do

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Hi,

I create my project and block diagram from scratch using the TCL files generated by Vivado. When I load the project in (project TCL file + Block Design TCL file) I am able to launch xsim running the defaults and the launch_simulation command. When I select Questa as my default simulator and run the export_simulation command none of the IP blocks generated from my block design show up in the Compile.do.

If I first run xsim, change the simulation environment to Questa, and then run the export_simulation command everything seems to work fine (i.e. I can run the Questa testbench). What step is happening to generate that IP? I have also tried regenerating the IP from the Block Design but that didn't help.

Thanks,

Ari

Tool version information:

Vivado 2019.1

Questa 10.7c

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bandi
Moderator
Moderator
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Registered: ‎09-15-2016

Hi @amahpour ,

Can you please make sure that you have regenerated the output products of the block design before launching export_simulation command. Then try generating the scripts and run simulation.

Thanks & Regards,
Sravanthi B
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bandi
Moderator
Moderator
682 Views
Registered: ‎09-15-2016

Hi @amahpour ,

Can you please make sure that you have regenerated the output products of the block design before launching export_simulation command. Then try generating the scripts and run simulation.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
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amahpour
Observer
Observer
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Registered: ‎01-28-2015

Are you referring to the generate IP block command that generates the IP for sim and synthesis? If so, I do that as well (first) in my TCL script and it still doesn’t work. 

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amahpour
Observer
Observer
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Registered: ‎01-28-2015

Actually that worked. For the record the command was:

generate_target simulation [get_files  <path to bd file>.bd]

Is there a way to get the bd name without having to specify the full path? I tried the get_bd_designs command but that didn't seem to work for me.

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