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prateekmohan
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Registered: ‎11-10-2020

Xilinx ISE 14.7 Internal Compiler Error

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Hello,

I am trying to run a simulation using Xilinx ISE 14.7 (The FPGA I am synthesizing for is a Spartan 6, so I can't use Vivado) and I am running into a FATAL_ERROR:

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VlogDecl.cpp at line 1483 For technical support on this issue, please visit http://www.xilinx.com/support.

The line right before this is:

Completed static elaboration
Fuse Memory Usage: 101404 KB
Fuse CPU Usage: 1200 ms
Compiling module memc3_infrastructure_sim(C_MEMCL...
FATAL_ERROR:Simulator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VlogDecl.cpp at line 1483 For technical support on this issue, please visit http://www.xilinx.com/support.
FATAL_ERROR:Simulator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VlogDecl.cpp at line 1483 For technical support on this issue, please visit http://www.xilinx.com/support.

The module that it is referring to (memc3_infrastructure_sim) is actually an empty module - it just has a module declaration. I removed the inner code in hopes it was related to the code inside it but that doesn't seem to be the case either. 

Thanks in advance for the help!

Prateek

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prateekmohan
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Registered: ‎11-10-2020

I'm closing this ticket - I was able to compile by just creating a simulation model of this block outside the Verilog DUT. 

Prateek

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prateekmohan
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Registered: ‎11-10-2020

I'm closing this ticket - I was able to compile by just creating a simulation model of this block outside the Verilog DUT. 

Prateek

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