03-11-2021 09:20 AM - edited 03-11-2021 10:30 AM
During Xsim elaboration, I get the following error:
ERROR: [XSIM 43-3241] File /wrk/2019.1/continuous/2019_05_24_2552052/data/secureip/gthe4_channel/gthe4_channel_002.vp, Line Num 22720, Node SIM_VERSION is not annotated.
There is also this warning which may be related:
WARNING: [VRFC 10-4969] module 'SIP_GTHE4_CHANNEL' is instantiated multiple times from VHDL or from both Verilog and VHDL, elaboration result may be incorrect [/wrk/2019.1/continuous/2019_05_24_2552052/data/secureip/gthe4_channel/gthe4_channel_001.vp:16]
The project completes synthesis and implementation without errors. How do I fix this elaboration error?
My elaboration log file is attached.
03-11-2021 06:11 PM
There used to be an issue with mixed-language design related to this SIM_VERSION parameter. But it should have been fixed in 2018.3.
Did you generate all IPs in 2019.1?
Please also try to generate Verilog output files for block design or IPs? i.e. set the target language to Verilog
03-12-2021 07:32 AM
Yes, all IP was generated in 2019.1. I have tried doing a "reset_project" and generating outputs to Verilog, but the elaboration error still occurs. I'm running on a Linux machine if that makes a difference.
Any other suggestions?
03-14-2021 07:09 AM
Hi @kinkeads ,
Can you please share the archived project or the test case to check this issue at our end?
04-13-2021 11:16 AM
How do I send you my archived project so it private and not shared with the forum community?
BTW, I determined that the elaboration error only occurs when I set the simulation top module to be my System Verilog testbench. If I set the simulation top module to be my FPGA top, Xsim starts o.k.
04-15-2021 03:28 AM
Hi @kinkeads ,
I have shared an EZMove FTP link. Can you please attach the archived file to that and send it to me.