cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
kinkeads
Adventurer
Adventurer
704 Views
Registered: ‎12-20-2010

Xsim elaboration error

During Xsim elaboration, I get the following error:

ERROR: [XSIM 43-3241] File /wrk/2019.1/continuous/2019_05_24_2552052/data/secureip/gthe4_channel/gthe4_channel_002.vp, Line Num 22720, Node SIM_VERSION is not annotated.

There is also this warning which may be related:

WARNING: [VRFC 10-4969] module 'SIP_GTHE4_CHANNEL' is instantiated multiple times from VHDL or from both Verilog and VHDL, elaboration result may be incorrect [/wrk/2019.1/continuous/2019_05_24_2552052/data/secureip/gthe4_channel/gthe4_channel_001.vp:16]

The project completes synthesis and implementation without errors.  How do I fix this elaboration error? 

My elaboration log file is attached.

 

0 Kudos
7 Replies
drjohnsmith
Teacher
Teacher
687 Views
Registered: ‎07-09-2009

cant see any files 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
kinkeads
Adventurer
Adventurer
671 Views
Registered: ‎12-20-2010

Ooops.  The elaboration.log file should be visible in the first post now.

0 Kudos
graces
Moderator
Moderator
630 Views
Registered: ‎07-16-2008

There used to be an issue with mixed-language design related to this SIM_VERSION parameter. But it should have been fixed in 2018.3.

Did you generate all IPs in 2019.1?

Please also try to generate Verilog output files for block design or IPs? i.e. set the target language to Verilog

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
kinkeads
Adventurer
Adventurer
589 Views
Registered: ‎12-20-2010

Yes, all IP was generated in 2019.1.   I have tried doing a "reset_project" and generating outputs to Verilog, but the elaboration error still occurs.  I'm running on a Linux machine if that makes a difference.

Any other suggestions?

0 Kudos
bandi
Moderator
Moderator
536 Views
Registered: ‎09-15-2016

Hi @kinkeads ,

Can you please share the archived project or the test case to check this issue at our end?

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
kinkeads
Adventurer
Adventurer
422 Views
Registered: ‎12-20-2010

How do I send you my archived project so it private and not shared with the forum community?

BTW, I determined that the elaboration error only occurs when I set the simulation top module to be my System Verilog testbench.  If I set the simulation top module to be my FPGA top, Xsim starts o.k. 

0 Kudos
bandi
Moderator
Moderator
393 Views
Registered: ‎09-15-2016

Hi @kinkeads ,

I have shared an EZMove FTP link. Can you please attach the archived file to that and send it to me.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos