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Visitor
Visitor
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Registered: ‎12-02-2020

Zynq MPSOC ZCU102

Hi,

I hope someone can help. I have been pretty frustrated with this issue. I am new to vivado block design.

i used an example project walk through from Xilinix that uses Zynz Ultrascale+ MPSoC with Axi SmartConnect to a Axi Bram controller that is tied to a dual port block ram.

I was able to verify writes using Zync_VIP commands as a test bench in system verilog simulation. However i tried to add a custom RTL module. This module is tied to port B of dual port ram. I am unable to see the signals of this custom RTL module in simulation scope. The module shows up in design sources and is in the block design.

I first thought the block was being optimized out so i turned of optimization using xelab -O0 arguments.

 

i hope this is enough information for you to help. Thank you!

 

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Participant
Participant
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Registered: ‎05-24-2020

@sbagga89 

Is it possible to post a screenshot of the vivado block design ?

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