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Observer kuldipspx
Observer
5,752 Views
Registered: ‎08-09-2012

Zynq VIP AR67207

The link to the AR67207 in DS940 is incorrect. Please provide the correct link to the Zynq VIP example design.

thanks

kuldip

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13 Replies
Moderator
Moderator
5,713 Views
Registered: ‎11-09-2015

Re: Zynq VIP AR67207

Hi @kuldipspx,

 

You may want to look at PG267 (link) instead. It is more complete and has the correct AR (AR#68234).

 

I will check if the DS940 was supposed to be published (for example, it cannot be found on DocNav)

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer kuldipspx
Observer
5,552 Views
Registered: ‎08-09-2012

Re: Zynq VIP AR67207

Please provide Zynq VIP based example design. I want to update my simulation testbench from Zynq BFM to Zynq VIP.

thanks

kuldip

Moderator
Moderator
5,535 Views
Registered: ‎11-09-2015

Re: Zynq VIP AR67207

Hi @kuldipspx,

 

This is in the AR -> link

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor lishixing
Visitor
4,528 Views
Registered: ‎10-28-2017

Re: Zynq VIP AR67207

Have you solved your problem?
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Visitor lishixing
Visitor
4,458 Views
Registered: ‎10-28-2017

Re: Zynq VIP AR67207

I also want to update my simulation testbench from Zynq BFM to Zynq VIP.Can you give me a testbench example?
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Moderator
Moderator
4,451 Views
Registered: ‎11-09-2015

Re: Zynq VIP AR67207

Hi @lishixing,

 

1. If you have an issue, you should create a new post on the forums.

 

2. If you need an example to use the VIP: add the VIP to a BD. In the source window, find the VIP, right click on it > generate example desing. You will have example test benches.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor lishixing
Visitor
4,327 Views
Registered: ‎10-28-2017

Re: Zynq VIP AR67207

Hi@florentw

1.My problem is similar to his.

2.I want use "Zynq-7000 All Programmable SoC Verification IP v1.0" this ip.I hope to use the function of the figure below.The Zynq-7000 VIP will automatically be delivered as part of the Zynq Processing System block simulation source. So,I can not find a testbench example.

1510903814(1).png

 

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Observer mferraro
Observer
4,224 Views
Registered: ‎01-20-2009

Re: Zynq VIP AR67207

I also have the same request.

 

Florent > you are providing links and references to the AXI VIP.   This question is about ZYNQ VIP.  These are two different simulation models.  With the Zynq VIP; the 'right click generate example design is not available'

 

lishixing > you can get example test bench by going

File -> Open Example Project > Base Zynq

Then look at zynq_tb.v : 

 

tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h0);

//This drives the LEDs on the GPIO output
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.write_data(32'h41200000,4, 32'hFFFFFFFF, resp);
$display ("LEDs are toggled, observe the waveform");
//Write into the BRAM through GP0 and read back
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.write_data(32'h40000000,4, 32'hDEADBEEF, resp);
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.read_data(32'h40000000,4,read_data,resp);
$display ("%t, running the testbench, data read from BRAM was 32'h%x",$time, read_data);

Moderator
Moderator
4,213 Views
Registered: ‎11-09-2015

Re: Zynq VIP AR67207

HI @mferraro,

 

You are right I have mixed between the AXI VIP and the zynq VIP. Thank you for sharing a way to have a test bench.

 

The correct AR is AR#69031

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor hypze
Visitor
3,107 Views
Registered: ‎12-08-2017

Re: Zynq VIP AR67207

       Using this example design,add some code to zynq_tb.v.I want to read data from "img.txt",through the HP ports. No data obtain. 

 

       //Reset the PL
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h0);
              
        /////    zynq  vip
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.set_slave_profile("S_AXI_HP0",2'b00);
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.set_channel_level_info("ALL",0);
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.set_function_level_info("ALL",0);
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.set_debug_level_info(0);                      
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.pre_load_mem_from_file("img.txt",32'h0100_0000,102400);
       
        //This drives the LEDs on the GPIO output
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.write_data(32'h41200000,4, 32'hFFFFFFFF, resp);
        $display ("LEDs are toggled, observe the waveform");
        //Write into the BRAM through GP0 and read back
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.write_data(32'h40000000,4, 32'hDEADBEEF, resp);
        tb.zynq_sys.base_zynq_i.processing_system7_0.inst.read_data(32'h40000000,4,read_data,resp);

 

1512790127(1).png

 

 

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Observer mferraro
Observer
3,059 Views
Registered: ‎01-20-2009

Re: Zynq VIP AR67207

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Visitor seiranp
Visitor
2,253 Views
Registered: ‎05-04-2018

Re: Zynq VIP AR67207

Hi Florent , is any way to disable/enable messages into TCL window from ZYNQ VIP API ?
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Moderator
Moderator
2,207 Views
Registered: ‎11-09-2015

Re: Zynq VIP AR67207

HI @seiranp,

 

Our Community Help has a tip that might help you : Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

 

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

I would suggest you create a new topic on the appropriate board. This is a different question, I will not reply to this topic.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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