10-11-2018 04:00 AM
just after a 2018.2.1 to 2018.2.2 Vivado updating all my simulations fail
ERROR: [VRFC 10-149] 'axi_vdma' is not compiled in library axi_vdma_v6_3_5
Also if I create a new project, create a Block Design, instantiate an axi_vdma inside it and
simply Open an IP example and I try to simulate what the tool automatically generates,
simulation fails this time with message
ERROR: [VRFC 10-149] 'axi_bram_ctrl' is not compiled in library axi_bram_ctrl_v4_0_14
Before downgrade Vivado I ask if it is a known issue and if there is a workaround
10-11-2018 04:23 AM - edited 10-11-2018 04:23 AM
Have you re compile / update all the cores in the design using the newer vivado you have ?
10-11-2018 04:47 AM
Please share xci file of axi_vdma to reproduce the issue at our end.
10-11-2018 04:51 AM
10-11-2018 04:59 AM
Did you check if the library window is correctly displaying the files?
10-11-2018 12:15 PM
Unfortunally I can't share my original project vdma xci file, BUT
it is very easy reproduce the issue.
Just opened Vivado 2018.2.2
I entered these commands:
create_project project_9 <my_dir>/project_9 -part xc7a100tfgg676-2L
set_property target_language VHDL [current_project]
update_compile_order -fileset sources_1
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0
open_example_project -force -dir <my_dir> [get_ips design_1_axi_vdma_0_0]
and inside the project axi_vdma_0_ex I simply launched simulation
and ...BOOOM, the problem soon arise with these messages
ERROR: [VRFC 10-149] 'axi_bram_ctrl' is not compiled in library axi_bram_ctrl_v4_0_14 [c:/Users/V/Documents/VIVADO_PROJECTS/axi_vdma_0_ex/axi_vdma_0_ex.srcs/sources_1/ip/axi_bram_ctrl_1/sim/axi_bram_ctrl_1.vhd:57]
INFO: [VRFC 10-307] analyzing entity axi_bram_ctrl_1
ERROR: [VRFC 10-1504] unit axi_bram_ctrl_1 ignored due to previous errors [c:/Users/V/Documents/VIVADO_PROJECTS/axi_vdma_0_ex/axi_vdma_0_ex.srcs/sources_1/ip/axi_bram_ctrl_1/sim/axi_bram_ctrl_1.vhd:59]
exactly in same way of my original project.
I attached xci, xml and vhd files generated by Vivado and my suspicion is that
it is a mismatch between xml and vhd files. In xml file there is, both in synthesis and in sim parts
instead in vhd files there is
but it is only a suspicions.
The same problem arises in two different OS (windows 8.1 and windows10)
10-12-2018 11:57 PM - edited 10-12-2018 11:58 PM
Now I downgraded my Vivado to 2018.2.1 and all seems run correctly.
If nobody else has experienced my issue perhaps something can went wrong during 2018.2.1 to 2018.2.2 updating
10-15-2018 12:44 AM
I have encountered the same kind of issue since I have upgraded my vivado version from 2018.2 to 20.18.2.
10-17-2018 03:12 AM
This issue will be fixed in upcoming version of VIVADO 2018.3.
Till then I will recommend you to stick to the 2018.2 version.
The only difference between the 2018.2 and 2018.2.2 is the addition of few devices in the list of supported device.
Please check below page for more information:
So it's not necessary for you to update to 2018.2.2 since 2018.2 already supports xc7a100tfgg676-2L.
Let us know if this helps.
11-21-2018 06:18 AM
Same error is observed for PCIe Example with AXI Bridge Configuration.
Do you know what's work around for this?
01-02-2019 09:39 PM
This is a known issue in 2018.2.2.
02-26-2019 04:40 PM
Have the same issue
Backward compatability is broken.