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vgobbi
Adventurer
Adventurer
2,981 Views
Registered: ‎10-20-2011

after 2018.2.1 to 2018.2.2 Vivado updating simulations fails with ERROR: [VRFC 10-149] ... is not compiled in library

Hi,

just after a 2018.2.1 to 2018.2.2 Vivado updating all my simulations fail

with message

ERROR: [VRFC 10-149] 'axi_vdma' is not compiled in library axi_vdma_v6_3_5

 

Also if I create a new project, create a Block Design, instantiate an axi_vdma inside it and

simply Open an IP example and I try to simulate what the tool automatically generates,

simulation fails this time with  message

ERROR: [VRFC 10-149] 'axi_bram_ctrl' is not compiled in library axi_bram_ctrl_v4_0_14

 

Before downgrade Vivado I ask if it is a known issue and if there is a workaround

 

Thanks

 

Vit

 

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12 Replies
drjohnsmith
Teacher
Teacher
2,970 Views
Registered: ‎07-09-2009

Have you re compile / update all the cores in the design using the newer vivado you have ?

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vgobbi
Adventurer
Adventurer
2,965 Views
Registered: ‎10-20-2011

Yes,
I have
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syedz
Moderator
Moderator
2,961 Views
Registered: ‎01-16-2013

@vgobbi

 

Please share xci file of axi_vdma to reproduce the issue at our end.

 

--Syed

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vgobbi
Adventurer
Adventurer
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Registered: ‎10-20-2011

More exactly, indeed,
just upon I had recompiled all that problem arises.
After updating I can simulate, but I had to make a change
in my rtl and next simulation end to run

Thanks
Vit
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syedz
Moderator
Moderator
2,948 Views
Registered: ‎01-16-2013

@vgobbi

 

Did you check if the library window is correctly displaying the files? 

Capture.JPG

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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vgobbi
Adventurer
Adventurer
2,922 Views
Registered: ‎10-20-2011

Unfortunally I can't share my original project vdma xci file, BUT

it is very easy reproduce the issue.

 

Just opened Vivado 2018.2.2

I entered these commands:

create_project project_9 <my_dir>/project_9 -part xc7a100tfgg676-2L
set_property target_language VHDL [current_project]
create_bd_design "design_1"
update_compile_order -fileset sources_1
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0
endgroup
save_bd_design
open_example_project -force -dir <my_dir> [get_ips  design_1_axi_vdma_0_0]

 

and inside the project axi_vdma_0_ex I simply launched simulation

 

and ...BOOOM, the problem soon arise with these messages

 

ERROR: [VRFC 10-149] 'axi_bram_ctrl' is not compiled in library axi_bram_ctrl_v4_0_14 [c:/Users/V/Documents/VIVADO_PROJECTS/axi_vdma_0_ex/axi_vdma_0_ex.srcs/sources_1/ip/axi_bram_ctrl_1/sim/axi_bram_ctrl_1.vhd:57]
INFO: [VRFC 10-307] analyzing entity axi_bram_ctrl_1
ERROR: [VRFC 10-1504] unit axi_bram_ctrl_1 ignored due to previous errors [c:/Users/V/Documents/VIVADO_PROJECTS/axi_vdma_0_ex/axi_vdma_0_ex.srcs/sources_1/ip/axi_bram_ctrl_1/sim/axi_bram_ctrl_1.vhd:59]

exactly in same way of my original project.

 

I attached xci, xml and vhd files generated by Vivado and my suspicion is that

it is a mismatch between xml and vhd files. In xml file there is, both in synthesis and in sim parts

..

        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>

...

instead in vhd files there is

LIBRARY axi_bram_ctrl_v4_0_14;
USE axi_bram_ctrl_v4_0_14.axi_bram_ctrl;

 

but it is only a suspicions.

 

The same problem arises in two different OS (windows 8.1 and windows10)

 

Thanks

-Vit

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vgobbi
Adventurer
Adventurer
2,894 Views
Registered: ‎10-20-2011

Now I downgraded my Vivado to 2018.2.1 and all seems run correctly.

 

If nobody else has experienced my issue perhaps something can went wrong during 2018.2.1 to 2018.2.2 updating

 

-Vit

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mick-board
Newbie
Newbie
2,857 Views
Registered: ‎07-26-2018

Hi Vgobbi,

 

I have encountered the same kind of issue since I have upgraded my vivado version from 2018.2 to 20.18.2.

 

Regards,

 

 

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kvasantr
Moderator
Moderator
2,818 Views
Registered: ‎04-12-2017

Hello @vgobbi and @mick-board,

 

This issue will be fixed in upcoming version of VIVADO 2018.3.

Till then I will recommend you to stick to the 2018.2 version.

 

The only difference between the 2018.2 and 2018.2.2 is the addition of few devices in the list of supported device.

Please check below page for more information:

https://www.xilinx.com/support/download.html

 

So it's not necessary for you to update to 2018.2.2 since 2018.2 already supports xc7a100tfgg676-2L.

 

Let us know if this helps.

Thank you.

 

 

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vj7
Observer
Observer
2,543 Views
Registered: ‎09-19-2018

Same error is observed for PCIe Example with AXI Bridge Configuration. 

Do you know what's work around for this?

 

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graces
Moderator
Moderator
2,222 Views
Registered: ‎07-16-2008

This is a known issue in 2018.2.2.

You can manually regenerate the missing xsim libs to work around the problem.
 
vivado -mode tcl
compile_simlib -simulator xsim -directory <path>
 
In the Vivado project, set this property to point to re-compiled simulation library:
set_property compxlib.xsim_compiled_library_dir <path> [current_project]
 
Then re-launch simulation.
 
Alternatively, you can upgrade to 2018.3 in which the problem is not seen.
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hayk.petr
Adventurer
Adventurer
1,781 Views
Registered: ‎10-04-2018

Have the same issue

Backward compatability is broken.

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