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alangford
Participant
Participant
1,744 Views
Registered: ‎06-15-2017

any way to avoid recompiling entire codebase for simulation

Hi,

 

Using Vivido 2017.2 with ISim on Windows 10

 

Im putting a test bench together that includes "encrypted" source code IP from a third party vendor. The design within the IP is quite large (~ 20% of a Zynq-7000 device)

 

Im finding that every time I make a change to my test bench and wish to re-run the simulation (which I do using "relaunch simulation") the tool goes away and recompiles & elaborates my entire codebase, including the design in the IP core, even though the source code has not changed. Because the design is quite big, this is taking a frustratingly long amount of time.

 

I've had a look through the settings but can't find anything that seems it would stop the tool from doing a global recompile every time I relaunch the sim.

 

Any suggestions are greatly appreciated!

 

Thanks

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6 Replies
thakurr
Moderator
Moderator
1,719 Views
Registered: ‎09-15-2016

Hi @alangford

 

Relaunch simulation is expected to recompile the simulation sources and restart the simulation. Since all the files from design sources are by default included in the simulation fileset hence it will recompile the entire files including test bench and design sources.

See if un-checking the below option helps you.

uncheck_sim.PNG

 

Regards

Rohit

Regards
Rohit
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drjohnsmith
Teacher
Teacher
1,709 Views
Registered: ‎07-09-2009

It is amazing,

 

software compiles sorted out a long time ago only to compile what was needed,

  

yet hardware, the equivalent longer to do tan a software compile, yet we still go for everything every time

 

very 1980's...

 

one day the simulation tools will take note of time stamps or whatever.

 

 

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alangford
Participant
Participant
1,696 Views
Registered: ‎06-15-2017

I found something that might help.

 

Under Settings > Project Settings > Simulation > Compilation there is a check-box (unchecked by default) for xsim.compile.incremental 

 

After checking this my compile time reduced from 9s to 1s ... however the tool is still taking close to a minute to run what it reports as "launch simulation" and during this phase, I still see messages indicating that its compiling the logic in the IP core I'm using, even though a previous message indicates that compilation is complete.

 

Hopefully ug900-vivado-logic-simulation will provide some insight - In there I see that its possible to enable incremental analysis/elaboration

 

 

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drjohnsmith
Teacher
Teacher
1,688 Views
Registered: ‎07-09-2009

well found

 

dont think simulation does elaboration though

 

 

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jmartinez
Adventurer
Adventurer
1,639 Views
Registered: ‎06-09-2016

you can try to modify design signals in tcl and just restart the simulation each time you want to modify some signals...

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drjohnsmith
Teacher
Teacher
1,634 Views
Registered: ‎07-09-2009

rule 1

 

with TCL you can solve anything...

 

 

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