cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
433 Views
Registered: ‎05-29-2018

automatic task and pass by reference with systemverilog on simulation

Dear,

On simulation, I want to write protocol behavior using automatic task statement with reference augments, which is a feature of systemverilog.
I used Vivado2019.2.

The problem is that "pass by reference" does not work well when I use task statement.

Vivado Design Suite User Guide - Logic Simulation (ug900)
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug900-vivado-logic-simulation.pdf

"static and Automatic task" and "Pass by reference" is supported, according to the document above (pp184).

To simplify what I want to write, I write pseude code here.

`timescale 1ns/1ns
module tb_sim();

task automatic task_a (
	ref logic [1:0]	a,
	const ref logic	b
);
	a = 2'b00;
	#100;
	if (b)
		a = 2'b10;
	else
		a = 2'd11;
	$display("step A: a = 0x%x, b = 0x%x", a, b);
	#1000;
	if (b)
		a = 2'b00;
	else
		a = 2'd01;
	$display("step B: a = 0x%x, b = 0x%x", a, b);
endtask


logic [1:0] aug;
logic sig;

initial begin
	sig = 1'b0;
	$display("step C: sig = 0x%x", sig);
	#800;
	sig = 1'b1;
	$display("step C: sig = 0x%x", sig);
end


initial begin
	$display("Simulation starts...");
	$display("======================================================");
	aug = 2'b00;
	#100;
	task_a(aug, sig);
	#200;
	#10;
	task_a(aug, sig);
	#200;
	$finish;
end

The result is below. Variable sig is going to be the second augment of task_a().
I expected that value of b on the first "step B" is 0x1, which sig's value varied.
This result means that "Pass by reference" does not work.
Just copying the augment to the variable on the task statement.

Simulation starts...
======================================================
step C: sig = 0x0
step A: a = 0x3, b = 0x0
step C: sig = 0x1
step B: a = 0x1, b = 0x0
step A: a = 0x2, b = 0x1
step B: a = 0x0, b = 0x1
$finish called at time : 2710 ns

Any idea for that? Am I wrong on how to use "pass by reference" ?

 

P.S. When I execute this on QuestaSim(10.7c), the result was like this.
This was what I expected.

# Simulation starts...
# ======================================================
# step C: sig = 0x0
# step A: a = 0x3, b = 0x0
# step C: sig = 0x1
# step B: a = 0x0, b = 0x1
# step A: a = 0x2, b = 0x1
# step B: a = 0x0, b = 0x1
# ** Note: $finish    : tb_sim.sv(48)

I hope this could work on vivado xsim as well.
If it is useful info or knowledge, please give me comments.


Best Regards,
toku1938

0 Kudos
0 Replies