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Observer
Observer
1,057 Views
Registered: ‎06-22-2016

axi_vip example design fails simulation

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Using Vivado 2018.2 and following this Vivado Qick Take video, the Behavioral Simulation fails.

 

The errors in the Tcl window are pasted below.

 

Starting static elaboration
ERROR: [VRFC 10-900] incompatible complex type assignment [../../../../imports/axi_vip_0_mst_stimulus.sv:81]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-99] Step results log file:'E:/axi_vip_0_ex/axi_vip_0_ex.sim/sim_adv_mst_active__pt_passive__slv_comb/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/axi_vip_0_ex/axi_vip_0_ex.sim/sim_adv_mst_active__pt_passive__slv_comb/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 1039.797 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

Thanks for the help.

1 Solution

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Moderator
Moderator
1,020 Views
Registered: ‎04-24-2013

Hi @hundley,

 

This can happen if the Target Language was set to VHDL instead of Verilog.

 

When you first open Vivado, make sure that the Target Language has been set to Verilog

 

Verilog.JPG

 

Then create the Block Design and open the IP Example Design as directed, it should now simulate without the error message.

 

I have attached the working version of the project for reference.

Best Regards
Aidan

 

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1 Reply
Highlighted
Moderator
Moderator
1,021 Views
Registered: ‎04-24-2013

Hi @hundley,

 

This can happen if the Target Language was set to VHDL instead of Verilog.

 

When you first open Vivado, make sure that the Target Language has been set to Verilog

 

Verilog.JPG

 

Then create the Block Design and open the IP Example Design as directed, it should now simulate without the error message.

 

I have attached the working version of the project for reference.

Best Regards
Aidan

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------

View solution in original post