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Observer bondylep
Observer
252 Views
Registered: ‎10-09-2018

axis fifo simulation s_axis_tready is alwasys low

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in my design ip instantiated a axis fifo,  simulation ok, s_axis_tready will high when aresetn released, but in my top project

instantiated my IP, then simulation  s_axis_tready will always low. which difference is that ,the aresetn is from processor reset module which will not reset when simulation start which will have simulation intialize problem, so i force the reset assert, and then released. 

I can not see any internal singal, i cannot debug it at all. is this any way to probe interanal singal?

I also simlate the example fifo IP, it is Ok, so i am much confused by it.

I used the *funsim.v to substitue it to simulate, it is ok.

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Observer bondylep
Observer
142 Views
Registered: ‎10-09-2018

Re: axis fifo simulation s_axis_tready is alwasys low

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it may be the cause that I force the reset singal, if i does not force, it is OK, but the root cause will not be known.

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Observer bondylep
Observer
229 Views
Registered: ‎10-09-2018

Re: axis fifo simulation s_axis_tready is alwasys low

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I force the aresetn low again and high, the s_axis_ready go high, I have long time aresetn low at start time of simulation.  there is enough time to reset it,  why it need reset twice?

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Observer bondylep
Observer
143 Views
Registered: ‎10-09-2018

Re: axis fifo simulation s_axis_tready is alwasys low

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it may be the cause that I force the reset singal, if i does not force, it is OK, but the root cause will not be known.

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