UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
10,816 Views
Registered: ‎12-09-2015

binding entity does not have generic

Jump to solution

Hi,

 

I have been struggling to find the problem. My code synthesizes and implementation runs fine as well but simulation always gives the same error which dosen't make sense to me.

 

[VRFC 10-380] binding entity \Counter\ does not have generic limit ["C:/Users/christopher/Counter_test/Counter_test.srcs/sim_1/imports/new/Counter_tb.vhd":25]

 

I don't understand this because the entity Counter does have the generic limit. It's right there. I have asked a few other people and they coulden't find the problem either. I am running Vivado 2015.4. Any ideas? 

 

Counter.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter is
generic (limit : integer := 10);
   port (clk : in  std_logic;
         rst : in  std_logic;
    rollover : out std_logic;
      enable : in  std_logic;
      output : out std_logic_vector(9 downto 0));
end Counter;

architecture behavioral of Counter is
signal temp: std_logic_vector(9 downto 0);

begin
    
     count : process ( clk, rst, temp, enable)
     
     begin
        
        --if one over target, indicate a rollover condition
          if(temp = limit+1) then
                 rollover <= '1';
           
           end if;
            
        --in the event of a reset signal or rollover reset the counter    
          if(temp = limit+1 OR rst = '1') then
            temp <= "0000000000";
       --increment the counter     
        elsif (clk'event and clk = '1' and enable = '1') then
            temp <= temp + 1; 
            rollover <= '0';              
        
        end if;
     
   end process count;     
       output <= temp; 
                
end behavioral;

 

Counter_tb.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter_tb is
end Counter_tb;

architecture testbench of Counter_tb is
  constant clock_hw_clock_period : time := 10 ns;
  signal   clk                 : std_logic;
  signal   rst                 : std_logic;
  signal   enable              : std_logic;
  signal   rollover            : std_logic;
  signal   output_h            : std_logic_vector(9 downto 0);
  signal   output_v            : std_logic_vector(9 downto 0);
  
  
  
  component Counter is
generic (limit : integer := 10);  
     port (clk : in  std_logic;
           rst : in  std_logic;
        enable : in  std_logic;
      rollover : out std_logic;
        output : out std_logic_vector(9 downto 0));
        
    end component;
    
    


begin
  

  -- horizontal counter counts to 799
  
 counter_h : Counter 
    generic map (limit => 799)
       port map (
            clk => clk,
            rst => rst,
         enable => enable, 
       rollover => rollover,
         output => output_h);
      
  -- vertical counter counts to 524      
 counter_v : Counter 
     generic map (limit => 524)
               port map (
             clk => clk,
             rst => rst,
          enable => rollover, --rollover of horizontal increments the vertical
          output => output_v);
  
   
  
  clock_hw_clock : process
  begin  -- process dff_hw_clock
    clk <= '0';
    wait for clock_hw_clock_period/2;
    clk <= '1';
    wait for clock_hw_clock_period/2;
  end process clock_hw_clock;

  clock_hw_stim_proc : process
  begin
    enable <= '1';
    --make an initial reset signal to zero out the counters
    rst <= '1';
   
    wait for (2*clock_hw_clock_period);
    
    rst <= '0';
    wait for (1000000000*clock_hw_clock_period);
    
    
    end process clock_hw_stim_proc;

end testbench;

 

0 Kudos
1 Solution

Accepted Solutions
19,781 Views
Registered: ‎12-09-2015

Re: binding entity does not have generic

Jump to solution

Hi,

 

Thanks for all the help. I understand what you guys are saying. I can't modify the file the way you guys are suggesting though (removing generics) since then the program dosen't serve its purpose, which is to have two of the same counters with different limits. It does compile, but dosen't do what I need.

 

At the same time I was also having issues with the compiler.

 

When I changed the project and made another behavioral file and instantiated the counters there the simulator diden't give any error but instead the compile hung at the executing compile step. I left it for 2 hours and it was still at the same step. 

 

I tried this many times and tried creating a new project but the same thing happened.

 

Sometimes the same thing would also happen when I removed the generics on the older project. Other times it worked but it took a while before it actually worked.

 

Anyway, I found the problem. It was with antivirus software. AVAST ANTIVIRUS was causing my simulation in Vivado 2015.4 to hang and never complete. When I disabled the antivirus software the problem went away and the project with instantiation of the counters into another behavioral file worked fine. 

 

View solution in original post

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
10,796 Views
Registered: ‎10-24-2013

Re: binding entity does not have generic

Jump to solution

Hi @themadhatter106

 

I just tried simulating your design with Vivado 2015.4 and see no issues.

Which version of tool are you using? Iam attaching the project archive for your reference.

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Capture.JPG
0 Kudos
Moderator
Moderator
10,790 Views
Registered: ‎07-01-2015

Re: binding entity does not have generic

Jump to solution

Hi @themadhatter106,

 

I am able to reproduce this issue in post-implementation-timimg simulation. I modified the testbench to the following test bench and it's working at my end.


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter_tb is
end Counter_tb;

architecture testbench of Counter_tb is
constant clock_hw_clock_period : time := 10 ns;
signal clk : std_logic;
signal rst : std_logic;
signal enable : std_logic;
signal rollover : std_logic;
signal output_h : std_logic_vector(9 downto 0);
signal output_v : std_logic_vector(9 downto 0);



component Counter is
--generic (limit : integer := 10);
port (clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
rollover : out std_logic;
output : out std_logic_vector(9 downto 0));

end component;

begin

-- horizontal counter counts to 799

counter_h : Counter
-- generic map (limit => 799)
port map (
clk => clk,
rst => rst,
enable => enable,
rollover => rollover,
output => output_h);

-- vertical counter counts to 524
counter_v : Counter
-- generic map (limit => 524)
port map (
clk => clk,
rst => rst,
enable => rollover, --rollover of horizontal increments the vertical
output => output_v);



clock_hw_clock : process
begin -- process dff_hw_clock
clk <= '0';
wait for clock_hw_clock_period/2;
clk <= '1';
wait for clock_hw_clock_period/2;
end process clock_hw_clock;

clock_hw_stim_proc : process
begin
enable <= '1';
--make an initial reset signal to zero out the counters
rst <= '1';

wait for (2*clock_hw_clock_period);

rst <= '0';
wait for (1000000000*clock_hw_clock_period);


end process clock_hw_stim_proc;

end testbench;

 

Please try the above code at your end and let us know.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
10,784 Views
Registered: ‎09-13-2014

Re: binding entity does not have generic

Jump to solution

Just to add few point what Arpan have posted

 

>> In post-synthesis/post-implementation, the generic(constant) are deleted and usage of those generic are replaced with constant value

>> In test bench, you had instance w.r.t to behavioral model(with generic involved) so the same test bench won't be applicable for post-synth/post-imple simulation, you need to modify like Arpan suggested

>> If you want to use same test bench for both behavioral as well as post-synth/post-impl., you need to do conditional instantiation under generate statement. Let us know if you need any help on this.

 

--dhiRAj

0 Kudos
19,782 Views
Registered: ‎12-09-2015

Re: binding entity does not have generic

Jump to solution

Hi,

 

Thanks for all the help. I understand what you guys are saying. I can't modify the file the way you guys are suggesting though (removing generics) since then the program dosen't serve its purpose, which is to have two of the same counters with different limits. It does compile, but dosen't do what I need.

 

At the same time I was also having issues with the compiler.

 

When I changed the project and made another behavioral file and instantiated the counters there the simulator diden't give any error but instead the compile hung at the executing compile step. I left it for 2 hours and it was still at the same step. 

 

I tried this many times and tried creating a new project but the same thing happened.

 

Sometimes the same thing would also happen when I removed the generics on the older project. Other times it worked but it took a while before it actually worked.

 

Anyway, I found the problem. It was with antivirus software. AVAST ANTIVIRUS was causing my simulation in Vivado 2015.4 to hang and never complete. When I disabled the antivirus software the problem went away and the project with instantiation of the counters into another behavioral file worked fine. 

 

View solution in original post

0 Kudos