cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
9,866 Views
Registered: ‎08-23-2008

can vivado generate verilog IPCORE simulation file?

Jump to solution

I use vivado generate 3 IPcore in my project, one is PLL, one is FIFO,one is RAM,but when i want to simulate my project i found the PLL files are verilog and the others are VHDL. I choose verilog language in my project, can I generate all IPcore in verilog language? how can i do it?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
18,741 Views
Registered: ‎09-20-2012

Hi @yongbyb2000

 

In Vivado 2015.3, 2015.4 the FIFO generator, block memory generator IP's deliver only VHDL simulation model irrespective of project settings. We are planning to deliver verilog model in our upcoming release vivado 2016.1. 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
18,742 Views
Registered: ‎09-20-2012

Hi @yongbyb2000

 

In Vivado 2015.3, 2015.4 the FIFO generator, block memory generator IP's deliver only VHDL simulation model irrespective of project settings. We are planning to deliver verilog model in our upcoming release vivado 2016.1. 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Highlighted
Contributor
Contributor
9,832 Views
Registered: ‎08-23-2008
OK,thanks
0 Kudos
Highlighted
Newbie
Newbie
1,744 Views
Registered: ‎02-22-2018

Hi Deepika,

 

Iam using Vivado v2016.3 (64-bit), but still iam not able to get verilog simulation files.

I have generated native FIFO and opened IP example design.

Simulation files in the Example Design are all vhdl files, and not sure how to generate verilog files.

Still there is no support for verilog in v2016.3?

 

Regards

Sunil Kumar

 

0 Kudos
Highlighted
Newbie
Newbie
1,700 Views
Registered: ‎02-22-2018

Hi Deepika,

 

I have generated native FIFO and opened IP example design.

All the source files were VHDL files.

Iam using Vivado v2016.3 (64-bit), iam not able to get verilog source files.

 

Also the simulation files in the Example Design are all vhdl files, and not sure how to generate verilog files.

Still there is no support for verilog in v2016.3?

 

Regards

Sunil Kumar

0 Kudos