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Visitor amol_aeva
Visitor
585 Views
Registered: ‎01-23-2018

clock must be initialized to 0 when using xpm_fifo

I spend more than a day trying to debug this so I thought I'd add this here in the hopes that someone else will find it useful. 

I am using an XPM_FIFO in my design configured in async mode. The wr_clk being driven from my testbench was created like this:

 

 

  logic wr_clk;

  initial begin
    wr_clk = 1'b1;
  end

  // 250MHz
  always #2 wr_clk = ~wr_clk;

When I run the simulation, the wr_rst_busy output from the fifo never goes low! After much trial and error, I found out that initializing the clock to 0 and not 1 makes everything work! Go figure. If anyone knows the logic behind this please chime in. This may be the case with other IP as well. 

 

initial begin
  wr_clk = 1'b0; // MUST BE 0!
end

 

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2 Replies
Scholar jmcclusk
Scholar
575 Views
Registered: ‎02-24-2014

Re: clock must be initialized to 0 when using xpm_fifo

Can you post a test case showing this behavior?   It will help to diagnose (and fix) this behavior.

Don't forget to close a thread when possible by accepting a post as a solution.
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Xilinx Employee
Xilinx Employee
511 Views
Registered: ‎09-20-2012

Re: clock must be initialized to 0 when using xpm_fifo

Hi @amol_aeva

 

I have seen a similar issue in the past when using vivado XSIM. The design works fine when using Questa simulator. I have filed CR 989523 to get this fixed. 

Thanks,
Deepika.
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