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Observer alexrp92
Observer
152 Views
Registered: ‎07-16-2019

clock simulation

 

I am trying to simulate the following circuit, I am focusing on the clock signals cause I have some critical errors in the implementation step. So I am trying to figure out why..

 

scheme.png

I have 2 questions about the simulation, 

simulacion.png

1) Why the output clock signal starts at 16 us? why there is an activation in the first 100 ns and 0 afterwads till 16 us? something like this happens with the second clock (it starts in the 17,7 us and the first input signal in the clock is in the 16 us)

2) My clocks.xdc is the following:

create_clock -period 10 -name adc_clk [get_ports adc_clk_p_i] 

set_input_delay -clock adc_clk -max 3.400 [get_ports {adc_dat_a_i[*]}]
set_input_delay -clock adc_clk -max 3.400 [get_ports {adc_dat_b_i[*]}]

create_clock -period 4.000 -name rx_clk [get_ports {daisy_p_i[1]}]

Why, if i set a period of 10 (I suppose to be ns), I get 100 ns in the simulation?

 

Thanks!

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Xilinx Employee
Xilinx Employee
118 Views
Registered: ‎07-16-2008

回复: clock simulation

The clk_out looks to be output of MMCM. Please monitor the 'locked' output signal. The output clock is not valid until locked is asserted.

The clock waveform is based on the actual clock configuration in the design. e.g. If it's a input clock, how is clock stimulus given in test bench? If it is output from clock modifying block like MMCM, it's determined by input clock frequency as well as MMCM setting.

Your constraint should also comply with the design.

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