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Adventurer
Adventurer
10,799 Views
Registered: ‎10-01-2014

clock wizard + DDS compiler - Simulation fails

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Hi guys,

 

I am trying to test and implement a DDS compiler using the IP catalog. To do so, I used the clock wizard to generate the clock and then I conect its output to the input of the DDS compiler, as it is showb in the fig:

 

Capture.PNGThen, I generated its output products and created a HDL wrapper to create the top level design in VHDL.

 

To test the design I created a testbench file. However I am wondering how can assign both differential clocks in the test bench document. I have done like this:

 

Capture2.PNG

Then after making sure that the sysnthesis and implementation is done without erros and run the simulation and got the following results:

Capture3.PNG

 

Can anyone tell me what I am doing wrong? In my option I think that the problem comes from the clock wizard, but I am not able to solve it.

 

Sorry if this is a quite begginer project, but I am just giving my first steps in Vivado and FPGAs.

 

PS: attached you my find my project.

 

Many thanks in advance,

 

Rodolfo

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Xilinx Employee
Xilinx Employee
19,901 Views
Registered: ‎08-02-2011
Oh I just noticed that you're in sin/cos LUT mode. In that case, you need to supply a phase at each clock cycle. It seems you left it unconnected and thus 0. sin(0)=0
www.xilinx.com

View solution in original post

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Xilinx Employee
Xilinx Employee
10,792 Views
Registered: ‎07-21-2014
Hi,

From what I understand is you want to have differential clock in test bench.
Can you try toggling Tclk_n pin in opposite polarity as that of Tclk_p in test bench itself?

-Shreyas
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Adventurer
Adventurer
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Registered: ‎10-01-2014

Hi aher,

 

Many thanks for your help, I changed the polarity of the clock signals in the test bench, as you can see:

 

Capture.PNG

 

However after running the simulation I am not getting the expected results, the output from the clock wizard (clk_out1) is always one. Do have any clue about what I am doing wrong?     

Capture2.PNG 

Many thanks,

 

Rodolfo

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Xilinx Employee
Xilinx Employee
10,778 Views
Registered: ‎08-02-2011

You only simulate a couple clock cycles and to avoid possible GSR sim issues, you should simulate at least 100ns before you expect meaningful results.

 

Try running for like 1 ms.

www.xilinx.com
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Adventurer
Adventurer
10,766 Views
Registered: ‎10-01-2014

Hi bwiec,

 

Many thanks for your help, now I am generating properly the clock signal. However, after running my simulation I am not getting the expected results on the output of the DDS block, as you can see:

 

 

Capture.PNG

 

To setup the DDS block I followed the configuration shown in the UG937 document without setting the controlo signal to ARESETn (active low), is this the reason that I am not getting the sine wave?

 

Moreover, to calculate the frequency of the sine wave according to the standard mode, I need to set the phase width and phase increment, but on the GUI of this IP core I have Phase width and output width. Are these input paramenters related with phase width and phase increment?

 

Many thanks,

Rodolfo

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Xilinx Employee
Xilinx Employee
19,902 Views
Registered: ‎08-02-2011
Oh I just noticed that you're in sin/cos LUT mode. In that case, you need to supply a phase at each clock cycle. It seems you left it unconnected and thus 0. sin(0)=0
www.xilinx.com

View solution in original post

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Adventurer
Adventurer
10,746 Views
Registered: ‎10-01-2014

Hi bwiec,

 

Thanks, make all sense. However I know that the phase increment is an unsigned constant value, do I have to define this variable in the s_axis_phase_tdata port of the DDS? 

 

Many thanks in advance,

 

Rodolfo

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Hello Rodolfo,

It's part of the s_axis_phase interface. Expand it and you can see the individual signals. The explanation of the interface exists in the PG.
www.xilinx.com
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Adventurer
Adventurer
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Registered: ‎10-01-2014

Hi bwiec,

 

I read all the information on the PG141 document. However, it is not clearly explained how can we assign the s_axis_phase_tdata bus for a specific frequency of the sinewave generated according to the SIN/COS LUT only configuration. I mean, in the first pages of the document it is well explained how we set different frequencies according to the phase increment and phase width, but when it comes to the implementation it is not explained the relation between the  s_axis_phase_tdata bus and these features.

 

Moreover, I had a look into the tutorial from the UG937 document and what they do is incrementing the s_axis_phase_tdata value in each rising clock cycle, however it is not explained which phase increment value is used and the relation between the sine wave frequency.

 

I also tried to adapt their code to mine, but instead of getting a sine wave I got a triangular wave, as you can see:

 

Capture3.PNG

 

 

My IP core and top level designs were updated to:

 

Capture2.PNG

 

Capture.PNG

Can you please let me know what I am doing wrong? and how the phase increment is set based on the s_axis_phase_tdata? I believe it is through the increment of count, but imagine if I wanted an increment of 12 (decimal) what I would have to do?

 

Many thanks in advance,

 

Rodolfo

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Xilinx Employee
Xilinx Employee
10,714 Views
Registered: ‎08-02-2011

Hi Rodolfo,

 

You are getting very close! The reason your plot is a triangular wave is because you're only incrementing up to ~44482 with your phase input, but it's 20 bits. So it goes from 0 to 2^20-1 = 1048575. So you're only looking at a small percentage of the sine wave.

 

When you use sin/cos lut mode, the output frequency is totally up to you how you drive phase tdata. Your resolution is a function of the ROM depth (which is, in turn, a function of your setting of the phase_in width when you generate the core).

 

If you want to increment by a higher number (which has the effect of higher frequency with lower resolution), simply change count <= count + 1 to count <= count + 12. Doing this will cause you to skip ROM table entries and thus get through the whole thing much faster.

www.xilinx.com
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Adventurer
Adventurer
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Registered: ‎10-01-2014

Hi bwiec,

 

Apparently it is working now! 

 

Capture.PNG

 

Many thanks! I really apreciatte your help!

 

Rodolfo

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