12-25-2017 11:24 PM
I wrote a VHDL code for synchronous demodulation. I use vivado 2016.4. it works perfectly with a testbench in the software. but when I burnt the code into the FPGA board (Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)) it doesnt work. any suggestions?
I used a software called tera term to read the output from the board. it is serial communication. nothing is wrong with the board. I tested the board with a different code and it worked. since it works fine in the simulation i couldn't find the error in my code.
12-26-2017 12:15 AM
did you add timing constraints?
you can put ILA for debug
12-26-2017 01:54 AM
Sounds like you need some hardware debugging. Put an oscilloscope on the TX pin and see if anything is happening; if you're getting data out but it's not showing up on the PC then you've probably just got the baud rate wrong (very easy to do).
If there's no data coming out, change the code to do a simple flashing LED output. Does that work? If not, you're probably using either the wrong clock pin or the wrong output pin. If it does work, connect that LED to an intermediate step in the process and see if it still works.
12-26-2017 02:08 AM
yea, i verified my transmitter with the oscilloscope. it is working properly. and the baud rate i am working with is 115200. that one also verified. actually i am getting all zero in my out put. even if i connect the signal or not!!
i implemented the code and took a timing report. it says all user specified timing constraints are met. now i am in a dead end. i really don't know how to debug my code!
12-26-2017 03:07 AM
ILA is a IP block that you can add to you code in the xilinx tools.
Its a logic analyser, that can grab data from inside the fpga in real time, and store.
then you can look at the data stored, using the JTAG port on the chip and the xilinx tools.