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Visitor grinaldi
Visitor
225 Views
Registered: ‎10-28-2015

combinatorial loop simulation issue

Hello,

I have multiple combinatorial loops in my design (and they are there on porpuse) but I am not able to start the simulation because I have X's due to those loops. Does Vivado simulator has any capability to resolve the X's to either 1's or 0's or random at time zero?

Any suggestions beside adding reset logic to force the state?

Thanks,

Giacomo

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3 Replies
Scholar drjohnsmith
Scholar
212 Views
Registered: ‎07-09-2009

Re: combinatorial loop simulation issue

Whats your language . can you share the code ?

in VHDL , for signal fred

signal fred : std_logic := '1';

BTW: combitational loops ?

Are you certain thats what you want ?

Rember simulation , is either delta times , so you have no timing info, or post P&R , in which case you will have timing,

This request often turns up with people wanting to do ring oscilators on chip,

the things to remember at the minimum, is the tools will simplify your logic, if you have 9 inverters in ring, the tools will optimise this to one inverter, A lot faster but may not be what you want.

There are lots of posts on this if its what your after.
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Visitor grinaldi
Visitor
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Registered: ‎10-28-2015

Re: combinatorial loop simulation issue

Thank you for the reply.

I am instantiating LUTs directly and instructing the tool not to touch them.

It is structural verilog code, so I cannot really initialize it, because it is composed by NAND/NORs that I describe them directly with LUTs and create loops connecting the output signals to the inputs. Here is an example of one cell:

(* RLOC = "X0Y0", DONT_TOUCH = "TRUE" *)
LUT2_L #(
.INIT(4'h7) // NAND
) NAND1 (
.LO(c1), // 
.I0(A), //
.I1(Q) // 
);

With other simulator I don't see any issue becaue they have the capability to initialize properly combinatorial loops, but I couldn't find any solution with the Vivado simulator. Maybe there is some simulator setting not documented ...

 

Thanks,

Giacomo

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Scholar drjohnsmith
Scholar
199 Views
Registered: ‎07-09-2009

Re: combinatorial loop simulation issue

Yep this is a known feature of Verilog,

there are a few get arounds
https://electronics.stackexchange.com/questions/246270/initialize-variable-used-in-always-ff-block

https://forums.xilinx.com/t5/Other-FPGA-Architectures/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

Have you seen this
https://www.xilinx.com/support/documentation/application_notes/xapp872.pdf
it gives a much more predictable oscillator, also does not suffer from coupling,where one ring oscilator in the logic affects another near it,

this comes out if your doing crypto, as ring oscillators will tend to lock ... sort of nullifying the crypto ......



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