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kynthia9
Observer
Observer
15,012 Views
Registered: ‎01-18-2012

compile_simlib error again, after INCISIV version fix

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still have the error like :

compile_simlib -simulator ncsim -directory /user/nak/work/xlib/
Compiling libraries for 'ies' in '/user/nak/work/xlib/'
--> Compiling 'verilog.secureip' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/secureip'
> Compiled Path = '/user/nak/work/xlib//secureip'
> Log File = '/user/nak/work/xlib//secureip/.cxl.verilog.secureip.secureip.lin64.log'
--> Compiling 'verilog.secureip:verilog.axi_bfm' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/secureip/axi_bfm'
> Compiled Path = '/user/nak/work/xlib//secureip'
> Log File = '/user/nak/work/xlib//secureip/.cxl.verilog.axi_bfm.secureip.lin64.log'
compile_simlib[verilog.secureip:verilog.axi_bfm]: 0 error(s), 7 warning(s)

compile_simlib[verilog.secureip]: 0 error(s), 14 warning(s), 25.00 % complete


--> Compiling 'vhdl.unisim' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unisims'
> Compiled Path = '/user/nak/work/xlib//unisim'
> Log File = '/user/nak/work/xlib//unisim/.cxl.vhdl.unisim.unisim.lin64.log'
--> Compiling 'vhdl.unisim:vhdl.unimacro' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unimacro'
> Compiled Path = '/user/nak/work/xlib//unimacro'
> Log File = '/user/nak/work/xlib//unimacro/.cxl.vhdl.unimacro.unimacro.lin64.log'
compile_simlib[vhdl.unisim:vhdl.unimacro]: 1 error(s), 10 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unimacro)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unimacro)' in the log file compile_simlib.log for details of compilation error(s).

--> Compiling 'vhdl.unisim:vhdl.unifast' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unifast'
> Compiled Path = '/user/nak/work/xlib//unifast'
> Log File = '/user/nak/work/xlib//unifast/.cxl.vhdl.unifast.unifast.lin64.log'
compile_simlib[vhdl.unisim:vhdl.unifast]: 1 error(s), 8 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unifast)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unifast)' in the log file compile_simlib.log for details of compilation error(s).

compile_simlib[vhdl.unisim]: 3 error(s), 30 warning(s), 50.00 % complete


Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unisim)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unisim)' in the log file compile_simlib.log for details of compilation error(s).

--> Compiling 'verilog.unisim' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/verilog/src'
> Compiled Path = '/user/nak/work/xlib//unisims_ver'
> Log File = '/user/nak/work/xlib//unisims_ver/.cxl.verilog.unisim.unisims_ver.lin64.log'
--> Compiling 'verilog.unisim:verilog.unimacro' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/verilog/src/unimacro'
> Compiled Path = '/user/nak/work/xlib//unimacro_ver'
> Log File = '/user/nak/work/xlib//unimacro_ver/.cxl.verilog.unimacro.unimacro_ver.lin64.log'
compile_simlib[verilog.unisim:verilog.unimacro]: 0 error(s), 2 warning(s)

--> Compiling 'verilog.unisim:verilog.unifast' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/verilog/src/unifast'
> Compiled Path = '/user/nak/work/xlib//unifast_ver'
> Log File = '/user/nak/work/xlib//unifast_ver/.cxl.verilog.unifast.unifast_ver.lin64.log'
compile_simlib[verilog.unisim:verilog.unifast]: 0 error(s), 1 warning(s)

compile_simlib[verilog.unisim]: 0 error(s), 6 warning(s), 75.00 % complete


--> Compiling 'verilog.simprim' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/verilog/src/unisims'
> Compiled Path = '/user/nak/work/xlib//simprims_ver'
> Log File = '/user/nak/work/xlib//simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log'
compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 100.00 % complete


Copying setup file 'cds.lib' to '/user/nak/work/xlib//cds.lib' ...
Copying setup file 'hdl.var' to '/user/nak/work/xlib//hdl.var' ...

**********************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: ies *
* Compiled on: Thu Oct 30 12:07:22 2014 *
* *
**********************************************************************************************
* Library | Lang | Mapped Name(s) | Err#(s) | Warn#(s) *
*--------------------------------------------------------------------------------------------*
* secureip | verilog | secureip | 0 | 14 *
*--------------------------------------------------------------------------------------------*
* axi_bfm | verilog | secureip | 0 | 7 *
*--------------------------------------------------------------------------------------------*
* unisim | vhdl | unisim | 3 | 30 *
*--------------------------------------------------------------------------------------------*
* unimacro | vhdl | unimacro | 1 | 10 *
*--------------------------------------------------------------------------------------------*
* unifast | vhdl | unifast | 1 | 8 *
*--------------------------------------------------------------------------------------------*
* unisim | verilog | unisims_ver | 0 | 6 *
*--------------------------------------------------------------------------------------------*
* unimacro | verilog | unimacro_ver | 0 | 2 *
*--------------------------------------------------------------------------------------------*
* unifast | verilog | unifast_ver | 0 | 1 *
*--------------------------------------------------------------------------------------------*
* simprim | verilog | simprims_ver | 0 | 0 *
*--------------------------------------------------------------------------------------------*

ERROR: [Vivado 12-3591] compile_simlib failed to compile for ies with 5 errors.
compile_simlib: Time (s): cpu = 00:02:50 ; elapsed = 00:03:28 . Memory (MB): peak = 8446.527 ; gain = 0.008 ; free physical = 124063 ; free virtual = 230020
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

 

 

log file:

ncvhdl(64): 14.10-g041: (c) Copyright 1995-2014 Cadence Design Systems, DEBUG
DEFINE unimacro /user/nak/work/compxlib//unimacro
|
ncvhdl: *W,DLCPTH (./cds.lib,1): cds.lib Invalid path '/user/nak/work/compxlib/unimacro' (cds.lib command ignored).
DEFINE unifast /user/nak/work/compxlib//unifast
|
ncvhdl: *W,DLCPTH (./cds.lib,2): cds.lib Invalid path '/user/nak/work/compxlib/unifast' (cds.lib command ignored).
DEFINE unisims_ver /user/nak/work/compxlib//unisims_ver
|
ncvhdl: *W,DLCPTH (./cds.lib,3): cds.lib Invalid path '/user/nak/work/compxlib/unisims_ver' (cds.lib command ignored).
DEFINE unimacro_ver /user/nak/work/compxlib//unimacro_ver
|
ncvhdl: *W,DLCPTH (./cds.lib,4): cds.lib Invalid path '/user/nak/work/compxlib/unimacro_ver' (cds.lib command ignored).
DEFINE unifast_ver /user/nak/work/compxlib//unifast_ver
|
ncvhdl: *W,DLCPTH (./cds.lib,5): cds.lib Invalid path '/user/nak/work/compxlib/unifast_ver' (cds.lib command ignored).
DEFINE simprims_ver /user/nak/work/compxlib//simprims_ver
|
ncvhdl: *W,DLCPTH (./cds.lib,6): cds.lib Invalid path '/user/nak/work/compxlib/simprims_ver' (cds.lib command ignored).
DEFINE unimacro /user/nak/work/compxlib//unimacro
|
ncvhdl_p: *W,DLCPTH (./cds.lib,1): cds.lib Invalid path '/user/nak/work/compxlib/unimacro' (cds.lib command ignored).
DEFINE unifast /user/nak/work/compxlib//unifast
|
ncvhdl_p: *W,DLCPTH (./cds.lib,2): cds.lib Invalid path '/user/nak/work/compxlib/unifast' (cds.lib command ignored).
DEFINE unisims_ver /user/nak/work/compxlib//unisims_ver
|
ncvhdl_p: *W,DLCPTH (./cds.lib,3): cds.lib Invalid path '/user/nak/work/compxlib/unisims_ver' (cds.lib command ignored).
DEFINE unimacro_ver /user/nak/work/compxlib//unimacro_ver
|
ncvhdl_p: *W,DLCPTH (./cds.lib,4): cds.lib Invalid path '/user/nak/work/compxlib/unimacro_ver' (cds.lib command ignored).
DEFINE unifast_ver /user/nak/work/compxlib//unifast_ver
|
ncvhdl_p: *W,DLCPTH (./cds.lib,5): cds.lib Invalid path '/user/nak/work/compxlib/unifast_ver' (cds.lib command ignored).
DEFINE simprims_ver /user/nak/work/compxlib//simprims_ver
|
ncvhdl_p: *W,DLCPTH (./cds.lib,6): cds.lib Invalid path '/user/nak/work/compxlib/simprims_ver' (cds.lib command ignored).

ncvhdl_p: *F,NOLSTD: logical library name STD must be mapped to a design library [11.2].

 

 

 

INCISIV 14.1

PATCH g041

 

any other solve?

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1 Solution

Accepted Solutions
vuppala
Xilinx Employee
Xilinx Employee
24,588 Views
Registered: ‎04-16-2012

Hello,

 

Try these steps to resolve the issue.

 

1. Point the first line of cds.lib file (located in '/user/nak/work/xlib/ directory) to the location of cds.lib file of ius installation

i.e., INCLUDE /vl/edatools/tools.lnx86/inca/files/cds.lib

2. Next navigate to /user/nak/work/xlib/unisim and run .cxl.vhdl.unisim.unisim.lin64.cmd

3. If it says permission denied, change the file permissions using the command: chmod +x '/user/nak/work/xlib/unisim and then run.

 

Repeat 2 and 3 steps for unifast and unimacro as well.

 

Note: Do not run compile_simlib after following these steps. It will override above edited files.

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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12 Replies
vijayak
Xilinx Employee
Xilinx Employee
15,001 Views
Registered: ‎10-24-2013
Hi,
Can you please try with Cadence Incisive Enterprise
Simulator (IES) (13.20.005) as this is the supported one with Vivado 2014.3
Thanks,Vijay
--------------------------------------------------------------------------------------------
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kynthia9
Observer
Observer
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Registered: ‎01-18-2012

still the same error

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vijayak
Xilinx Employee
Xilinx Employee
14,987 Views
Registered: ‎10-24-2013
Hi,
Can you please use the following command see if this helps.
-simulator ncsim is incorrect. You need to use ies as keyword

compile_simlib -language all -dir {/a/b/c} -simulator ies -simulator_exec_path {<simulator_installation_path>} -library all -family all
Thanks,Vijay
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kynthia9
Observer
Observer
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Registered: ‎01-18-2012

the same error

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kynthia9
Observer
Observer
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Registered: ‎01-18-2012

compile_simlib -language all -dir {/user/nak/work/xlib} -simulator ies -simulator_exec_path {/vl/edatools/bin} -library all -family all
Compiling libraries for 'ies' in '/user/nak/work/xlib'

Library verilog.secureip:verilog.axi_bfm will not be compiled, because precompiled library info is up to date.

Library verilog.secureip will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.secureip]: 0 error(s), 0 warning(s), 25.00 % complete

 

Library vhdl.unisim will be compiled, because precompiled library info is stale.
--> Compiling 'vhdl.unisim' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unisims'
> Compiled Path = '/user/nak/work/xlib/unisim'
> Log File = '/user/nak/work/xlib/unisim/.cxl.vhdl.unisim.unisim.lin64.log'

Library vhdl.unisim:vhdl.unimacro will be compiled, because precompiled library info is stale.
--> Compiling 'vhdl.unisim:vhdl.unimacro' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unimacro'
> Compiled Path = '/user/nak/work/xlib/unimacro'
> Log File = '/user/nak/work/xlib/unimacro/.cxl.vhdl.unimacro.unimacro.lin64.log'
compile_simlib[vhdl.unisim:vhdl.unimacro]: 1 error(s), 0 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unimacro)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unimacro)' in the log file compile_simlib.log for details of compilation error(s).


Library vhdl.unisim:vhdl.unifast will be compiled, because precompiled library info is stale.
--> Compiling 'vhdl.unisim:vhdl.unifast' library...
> Source Library = '/vl/edatools/extern/Xilinx/Vivado/2014.3/data/vhdl/src/unifast'
> Compiled Path = '/user/nak/work/xlib/unifast'
> Log File = '/user/nak/work/xlib/unifast/.cxl.vhdl.unifast.unifast.lin64.log'
compile_simlib[vhdl.unisim:vhdl.unifast]: 1 error(s), 0 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unifast)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unifast)' in the log file compile_simlib.log for details of compilation error(s).

compile_simlib[vhdl.unisim]: 3 error(s), 0 warning(s), 50.00 % complete


Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(ies:vhdl:unisim)' and 'END_COMPILATION_MESSAGES(ies:vhdl:unisim)' in the log file compile_simlib.log for details of compilation error(s).


Library verilog.unisim:verilog.unimacro will not be compiled, because precompiled library info is up to date.

Library verilog.unisim:verilog.unifast will not be compiled, because precompiled library info is up to date.

Library verilog.unisim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.unisim]: 0 error(s), 0 warning(s), 75.00 % complete

 

Library verilog.simprim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 100.00 % complete


Copying setup file 'cds.lib' to '/user/nak/work/xlib/cds.lib' ...

**********************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: ies *
* Compiled on: Fri Oct 31 15:50:36 2014 *
* *
**********************************************************************************************
* Library | Lang | Mapped Name(s) | Err#(s) | Warn#(s) *
*--------------------------------------------------------------------------------------------*
* unisim | vhdl | unisim | 3 | 0 *
*--------------------------------------------------------------------------------------------*
* unimacro | vhdl | unimacro | 1 | 0 *
*--------------------------------------------------------------------------------------------*
* unifast | vhdl | unifast | 1 | 0 *
*--------------------------------------------------------------------------------------------*

ERROR: [Vivado 12-3591] compile_simlib failed to compile for ies with 5 errors.
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

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vuppala
Xilinx Employee
Xilinx Employee
14,930 Views
Registered: ‎04-16-2012
Hello,

Attach compile_simlib.log file here.
Also which version of cadence incisive simulator are you using?

Thanks,
Vinay
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kynthia9
Observer
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14,923 Views
Registered: ‎01-18-2012

INCISIV 13.20, PATCH 005

 

I have ever tried INCISIV 14.1 g041 the same error.

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vuppala
Xilinx Employee
Xilinx Employee
24,589 Views
Registered: ‎04-16-2012

Hello,

 

Try these steps to resolve the issue.

 

1. Point the first line of cds.lib file (located in '/user/nak/work/xlib/ directory) to the location of cds.lib file of ius installation

i.e., INCLUDE /vl/edatools/tools.lnx86/inca/files/cds.lib

2. Next navigate to /user/nak/work/xlib/unisim and run .cxl.vhdl.unisim.unisim.lin64.cmd

3. If it says permission denied, change the file permissions using the command: chmod +x '/user/nak/work/xlib/unisim and then run.

 

Repeat 2 and 3 steps for unifast and unimacro as well.

 

Note: Do not run compile_simlib after following these steps. It will override above edited files.

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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View solution in original post

kynthia9
Observer
Observer
14,899 Views
Registered: ‎01-18-2012

yes, it works, but nee to edit .cmd file to point cds.lib and hdl.var to upper level where cds.lib and hds.var existed.

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wooki21
Visitor
Visitor
10,510 Views
Registered: ‎11-11-2014

Thank you.

 

I also had same problerm and resolved this.

But I don't know what is the root cause.

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jadeanderson
Visitor
Visitor
10,051 Views
Registered: ‎03-23-2015

I have tried this but I keep getting the same error.

ncvhdl: *F,DULEXE: cannot execute the VHDL analyzer (ncvhdl_p).

Any workaround for this?  


****************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: ies *
* Compiled on: Mon Mar 23 13:49:20 2015 *
* *
****************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*--------------------------------------------------------------------------*
* secureip | verilog | secureip | 0 | 0 *
*--------------------------------------------------------------------------*
* axi_bfm | verilog | secureip | 0 | 0 *
*--------------------------------------------------------------------------*
* unisim | vhdl | unisim | 3 | 0 *
*--------------------------------------------------------------------------*
* unimacro | vhdl | unimacro | 1 | 0 *
*--------------------------------------------------------------------------*
* unifast | vhdl | unifast | 1 | 0 *
*--------------------------------------------------------------------------*

ERROR: [Vivado 12-3591] compile_simlib failed to compile for ies with 5 errors.
compile_simlib: Time (s): cpu = 00:01:30 ; elapsed = 00:01:56 . Memory (MB): peak = 810.590 ; gain = 6.090 ; free physical = 26023 ; free virtual = 216884
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

 

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brendanlynskey
Visitor
Visitor
9,679 Views
Registered: ‎03-15-2013

I'm seeing the same problem with Vivado 2015.2.

 

Do you have a fix for this?

 

 - Bren

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