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Adventurer
Adventurer
729 Views
Registered: ‎11-07-2012

compile_simlib error when compiling for xcelium 19.03

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Hi 

Im compiling vivado libraries for xcelium 

using this tcl :

compile_simlib -simulator xcelium -simulator_exec_path {/pga/linux/Cadence/xcelium/19.03.009/bin} -family all -language all -library all -dir {/workspace/fpga_projects/xilinx_lib/vivado/vivado2019.1/XCELIUM19.03.009}

 

I get this msg error:


***********************************************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: xcelium *
* Compiled on: Wed Oct 23 14:31:43 2019 *
* *
***********************************************************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*---------------------------------------------------------------------------------------------------------------------*
* sync_ip | verilog | sync_ip | 1 | 1 *
*---------------------------------------------------------------------------------------------------------------------*

ERROR: [Vivado 12-5603] compile_simlib failed to compile for xcelium with error in 1 library (cxl_error.log)
INFO: [Vivado 12-7167] Writing compiled library information...
INFO: [Vivado 12-7165] Finished writing compiled library information.
compile_simlib: Time (s): cpu = 00:01:02 ; elapsed = 00:01:15 . Memory (MB): peak = 7884.445 ; gain = 0.000 ; free physical = 333645 ; free virtual = 478235
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

cxl_error.log: 

Library 'sync_ip' compilation error(s)
==============================================================================
xmvlog(64): 19.03-s009: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
file: /pga/linux/XILINX/VIVADO/2019.1/Vivado/2019.1/data/ip/xilinx/sync_ip_v1_0/hdl/sync_ip_v1_0_rfs.v
errors: 0, warnings: 0
xmvlog: *W,WARIPR: warning within protected source code.
errors: 0, warnings: 1
errors: 0, warnings: 0
errors: 0, warnings: 0
errors: 0, warnings: 0
errors: 0, warnings: 0
errors: 0, warnings: 0
errors: 0, warnings: 0
xmvlog: *E,ERRIPR: error within protected source code.
xmvlog: *E,ERRIPR: error within protected source code.
xmvlog: *E,ERRIPR: error within protected source code.
xmvlog: *E,ERRIPR: error within protected source code.
xmvlog: *E,ERRIPR: error within protected source code.
xmvlog: *E,ERRIPR: error within protected source code.
errors: 6, warnings: 0
errors: 0, warnings: 0

HELP,  PLS 

thank

yoti

 

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Moderator
Moderator
680 Views
Registered: ‎05-31-2017

Hi @yotam ,

As specified by Grace, this is a known issue. Please check the AR#72404 regarding the same.

View solution in original post

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Xilinx Employee
Xilinx Employee
698 Views
Registered: ‎07-16-2008

It is a known issue in 2019.1 that this specific IP fails compilation in IES/Xcelium.

If your design doesn't utilize this IP, please ignore the failure. The issue will be fixed in 2019.2.

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Highlighted
Moderator
Moderator
681 Views
Registered: ‎05-31-2017

Hi @yotam ,

As specified by Grace, this is a known issue. Please check the AR#72404 regarding the same.

View solution in original post

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Adventurer
Adventurer
669 Views
Registered: ‎11-07-2012

Hi 

can you tell me what this sync_ip use for?

for example - is it used to sync IPs in the block design?

there is no actual IP in the IP catalog calld sync_ip.

thanks

Yoti

 

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Xilinx Employee
Xilinx Employee
664 Views
Registered: ‎07-16-2008

The IP is targetting Zynq UltraScale+ and used in block design.

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Moderator
Moderator
661 Views
Registered: ‎05-31-2017

Hi @yotam ,

You need to target Zynq US+ device to see this IP in the IP catalog as shown in the below snippet

new1.jpg