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Explorer
Explorer
908 Views
Registered: ‎12-06-2013

compile_simlib failed to compile for active_hdl with <number> errors

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Any idea how to fix this?

TCL Console output:

 

start_guicompile_simlib -force -language vhdl -dir {<MY_PATH>.cache/compile_simlib} -simulator active_hdl -simulator_exec_path {C:/Aldec/Active-HDL 10.1/BIN} -library all -family  zynq

Compiling libraries for 'active_hdl' simulator in '<MY_PATH>.cache\compile_simlib'

ALIB: Library `secureip' attached.
secureip = <MY_PATH>.cache\compile_simlib\secureip\secureip.lib
--> Compiling 'verilog.secureip' library...
> Source Library = 'C:\Xilinx\Vivado\2015.4\data/secureip'
> Compiled Path  = '<MY_PATH>.cache\compile_simlib/secureip'
ERROR: [Common 17-180] Spawn failed: No error
> Log File = '<MY_PATH>.cache\compile_simlib/secureip/.cxl.verilog.secureip.secureip.nt64.log'
ALIB: Library `secureip' attached.
secureip = <MY_PATH>.cache\compile_simlib\secureip\secureip.lib
--> Compiling 'verilog.secureip:verilog.axi_bfm' library...
> Source Library = 'C:\Xilinx\Vivado\2015.4\data/secureip/axi_bfm'
> Compiled Path = '<MY_PATH>.cache\compile_simlib/secureip'
> Log File = '<MY_PATH>.cache\compile_simlib/secureip/.cxl.verilog.axi_bfm.secureip.nt64.log'
compile_simlib[verilog.secureip:verilog.axi_bfm]: 0 error(s), 9 warning(s)
compile_simlib[verilog.secureip]: 1 error(s), 31 warning(s), 50.00 % complete


Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(active_hdl:verilog:secureip)' and 'END_COMPILATION_MESSAGES(active_hdl:verilog:secureip)' in the log file compile_simlib.log for details of compilation error(s).

ALIB: Library `unisim' attached.
unisim = <MY_PATH>.cache\compile_simlib\unisim\unisim.lib
--> Compiling 'vhdl.unisim' library...
> Source Library = 'C:\Xilinx\Vivado\2015.4\data/vhdl/src/unisims'
> Compiled Path = '<MY_PATH>.cache\compile_simlib/unisim'
ERROR: [Common 17-180] Spawn failed: No error
> Log File = '<MY_PATH>.cache\compile_simlib/unisim/.cxl.vhdl.unisim.unisim.nt64.log'
ALIB: Library `unimacro' attached.
unimacro = <MY_PATH>.cache\compile_simlib\unimacro\unimacro.lib
--> Compiling 'vhdl.unisim:vhdl.unimacro' library...
> Source Library = 'C:\Xilinx\Vivado\2015.4\data/vhdl/src/unimacro'
> Compiled Path = '<MY_PATH>.cache\compile_simlib/unimacro'
ERROR: [Common 17-180] Spawn failed: No error
> Log File = '<MY_PATH>.cache\compile_simlib/unimacro/.cxl.vhdl.unimacro.unimacro.nt64.log'
compile_simlib[vhdl.unisim:vhdl.unimacro]: 1 error(s), 1 warning(s)
INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(active_hdl:vhdl:unimacro)' and 'END_COMPILATION_MESSAGES(active_hdl:vhdl:unimacro)' in the log file compile_simlib.log for details of compilation error(s).

ALIB: Library `unifast' attached.
unifast = <MY_PATH>.cache\compile_simlib\unifast\unifast.lib
--> Compiling 'vhdl.unisim:vhdl.unifast' library...
> Source Library = 'C:\Xilinx\Vivado\2015.4\data/vhdl/src/unifast'
> Compiled Path = '<MY_PATH>.cache\compile_simlib/unifast'
ERROR: [Common 17-180] Spawn failed: No error
> Log File = '<MY_PATH>.cache\compile_simlib/unifast/.cxl.vhdl.unifast.unifast.nt64.log'
compile_simlib[vhdl.unisim:vhdl.unifast]: 1 error(s), 1 warning(s)
INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(active_hdl:vhdl:unifast)' and 'END_COMPILATION_MESSAGES(active_hdl:vhdl:unifast)' in the log file compile_simlib.log for details of compilation error(s).

compile_simlib[vhdl.unisim]: 3 error(s), 3 warning(s), 100.00 % complete


Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(active_hdl:vhdl:unisim)' and 'END_COMPILATION_MESSAGES(active_hdl:vhdl:unisim)' in the log file compile_simlib.log for details of compilation error(s).


********************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: active_hdl *
* Compiled on: Fri Feb 16 08:08:49 2018 *
* *
********************************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*------------------------------------------------------------------------------------------*
* secureip | verilog | secureip | 1 | 31 *
*------------------------------------------------------------------------------------------*
* axi_bfm | verilog | secureip | 0 | 9 *
*------------------------------------------------------------------------------------------*
* unisim | vhdl | unisim | 3 | 3 *
*------------------------------------------------------------------------------------------*
* unimacro | vhdl | unimacro | 1 | 1 *
*------------------------------------------------------------------------------------------*
* unifast | vhdl | unifast | 1 | 1 *
*------------------------------------------------------------------------------------------*

ERROR: [Vivado 12-3591] compile_simlib failed to compile for active_hdl with 6 errors.
compile_simlib: Time (s): cpu = 00:00:01 ; elapsed = 00:00:18 . Memory (MB): peak = 590.871 ; gain = 9.621
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

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1 Solution

Accepted Solutions
Moderator
Moderator
1,280 Views
Registered: ‎09-15-2016

Re: compile_simlib failed to compile for active_hdl with <number> errors

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Hi @jeff_king,

 

I see that you are using 10.1 active HDL with vivado 2015.4. Can you please try using supported version of Active HDL 10.2SP2 and please let me know the outcome of it.

 

aldec.JPG

 

If you are still facing the issue then please share the compile_simlib.log and the secureip log file. Also, please make sure you are using supported OS with vivado 2015.4:

 

https://www.xilinx.com/support/answers/54242.html 

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
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2 Replies
Moderator
Moderator
1,281 Views
Registered: ‎09-15-2016

Re: compile_simlib failed to compile for active_hdl with <number> errors

Jump to solution

Hi @jeff_king,

 

I see that you are using 10.1 active HDL with vivado 2015.4. Can you please try using supported version of Active HDL 10.2SP2 and please let me know the outcome of it.

 

aldec.JPG

 

If you are still facing the issue then please share the compile_simlib.log and the secureip log file. Also, please make sure you are using supported OS with vivado 2015.4:

 

https://www.xilinx.com/support/answers/54242.html 

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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Explorer
Explorer
844 Views
Registered: ‎12-06-2013

Re: compile_simlib failed to compile for active_hdl with <number> errors

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@bandi I am running this on Windows 10 so that must be the problem. I tried creating the libraries again for 10.2 with errors but since the OS isn't supported I will try upgrading to a later version of Vivado. If all else fails, read the manual, eh? Lol, thanks for your help!

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