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Visitor
Visitor
5,895 Views
Registered: ‎09-22-2010

concept behind concurrent statements

we are learning that in data flow modelling all the statements are executed concurrently while in behav. it is sequentially...

 

can u pls explain while executing concurrent statament compiler is at more than one place at any time!!!!

 

how this is possible?? 

 

thanx!!

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Scholar
Scholar
5,885 Views
Registered: ‎02-27-2008

d,

 

Hardware may have (and often does have) many elements, each element may operate at the same time (concurrent).


Imagine four 2 input NAND gates, they will provide four outputs, of the four dual inputs, all at the same time.


If you program hardware, you use a Hardware Description language (like verilog, or VHDL).  Hardware can do as much as you require, all at one time, so you describe everything that you need to have done.  The synthesis tool (not a compiler) builds the circuits, and connects them to perdform the designed task.

 



Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
5,877 Views
Registered: ‎09-22-2010

but sir,

 

if we have the statements in the data flow modelling as:

 

c<=a and b;

d<=a xor c;

 

now i am not understanding how the simulater can execute these 2 statements at the same time... i mean how can a simulater be at 2 places at the same time????

 

thanx!!

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Visitor
Visitor
5,864 Views
Registered: ‎09-22-2010

more replies are invited
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Xilinx Employee
Xilinx Employee
5,854 Views
Registered: ‎01-03-2008

> now i am not understanding how the simulater can execute these 2 statements at the same time

 

The simulator is simulating a hardware implementation and hardware operates concurrently.  It isn't clear to my why you are concerned about ths.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Xilinx Employee
Xilinx Employee
5,851 Views
Registered: ‎11-28-2007

Concurrent statements are executed by the simulator concurrently in SIMULATION TIME not the cpu time. The simulator will still execute each statement sequentially in the processor (CPU time), but it will arrange/schedule statements in a way to match what would happend in HW (i.e. concurrently). Using your example, the simulator could execute the instructions below sequentially so that the signal d gets the "xor" result of a and c from the previous time tick.

 

c_last_tick = c;

c = a and b;

d = a xor c_last_tick;

 


@deep01 wrote:

but sir,

 

if we have the statements in the data flow modelling as:

 

c<=a and b;

d<=a xor c;

 

now i am not understanding how the simulater can execute these 2 statements at the same time... i mean how can a simulater be at 2 places at the same time????

 

thanx!!


 

Cheers,
Jim
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Historian
Historian
5,828 Views
Registered: ‎02-25-2008

 


@deep01 wrote:

but sir,

 

if we have the statements in the data flow modelling as:

 

c<=a and b;

d<=a xor c;

 

now i am not understanding how the simulater can execute these 2 statements at the same time... i mean how can a simulater be at 2 places at the same time????

 

thanx!!


 

You need to find a good VHDL book that explains the concept of "delta time" and simulation cycles.

 

----------------------------Yes, I do this for a living.
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Teacher
Teacher
5,809 Views
Registered: ‎08-14-2007

Hello deep01,

this is your animated simulator talking to you.

Let's simulate a very simple circuit consisting of two concurrent assingments like this:

 

c<=(a or b) after 10 ns;

e<=(d or c) and a;

 

The tesbench already told us to set all input's to '0'. (that is a, b and d), so the resulting signals c and e are also '0' now.

I won't explain how I reached this point now, but it's a good starting situation for our little simulation experience.

 

Since I am event driven, I will idle until something happens......

Oh, there's an event, coming on signal a at time T-0.

T_0: a <= '1'

Starting delta cycle 1:

Evaluate c<=a or b;    c<='1' scheduled for T_0 + 10ns

Starting delta cycle 2

Evaluate e<=(d or c) and a;  e <= '0'

 

That's all for this event, let's see what's on our list.... Ah, another  event at T_1 = T_0 + 10ns

T_1: c <= '1'

Starting delta cycle 1

Evaluate e<=(d or c) and a;  e <= '1'

 

Nothing more? Testbench finished?

Ok, lets write the results to the  waveform database, and terminate myself

Sayonara,

 your friendly neighborhood simulator. ;-)

 

Hope you got an idea.

Have a nice simulation

  Eilert

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