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Observer dlrmsqja1
Observer
1,120 Views
Registered: ‎05-29-2017

counter problem..

hi huys. this is my code. there are problem that encount doesn't add up. 

Attached figure is the image of simulation. Encount should be added up when counter_out reaches 210.

and encount will add up during en = 1'b1 and when en =1'b0, the code will be finished.

please help me why encount is stucked in 0?

-----------------------------------------------

module internal_counter(clk,counter_out,reset,clk_div_by_12,reset_sync);
input clk;
input reset;
output [13:0] counter_out;
output clk_div_by_12;
output reset_sync;
reg reset_sync;
reg [13:0] counter_out;
reg [8:0]encount;
reg en;
//creates a slow clock that is 2^13 of the input frequency.
assign clk_div_by_12 = counter_out[12];

 

always @(posedge clk) begin
counter_out <= 14'd0;
encount <= 9'd0;
if(counter_out < 14'd210 && en == 1'b1) begin
counter_out <= counter_out + 1;

end if(counter_out == 14'd210 && en == 1'b1) begin
counter_out <= 14'd0;
encount <= encount + 1;

end if(counter_out == 14'd210 && en == 1'b0) begin
counter_out <= 14'd0;

end if(counter_out < 14'd210 && en == 1'b0) begin
counter_out <= 14'd0;

end else if (reset) begin
counter_out <= 14'd0;
end

if (counter_out == 14'd0) begin
reset_sync <= 1'b1;
end else if (counter_out == 14'd1) begin
reset_sync <= 1'b1;
end else if (counter_out == 14'd2) begin
reset_sync <= 1'b1;
end else if (counter_out == 14'd3) begin
reset_sync <= 1'b1;
end else begin
reset_sync <= 1'b0;
end
end

////////////이게 문제//////////
always @(posedge clk) begin
if(encount == 9'd0) begin
en = 1'b1;
end if(encount < 9'd271) begin
en = 1'b1;
end else begin
en = 1'b0;

end
end
endmodule

 

 

제목 없음.png
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6 Replies
Moderator
Moderator
1,109 Views
Registered: ‎05-31-2017

Re: counter problem..

Hi @dlrmsqja1,

 

As per your logic, the encount value got incremented when counter_out=210 and en=1 as shown in the below snapshot. But as you have stated encount <= 9'd0; at the posedge clk, the encount value goes to 0 in the next clock cycle.



forum_count.JPG

 

Thanks & Regards,

A.Shameer.

Observer dlrmsqja1
Observer
1,088 Views
Registered: ‎05-29-2017

Re: counter problem..

@shameera thank you! for reply. maybe your simulation and my simulation result are different.

By attached file which is my result. there are no increment in encount....

this is the testbench code... #6.25 clk period is because OSC is 160MHz.

-----------------------

module internal_counter_tf;

// Inputs
reg clk;
reg reset;

// Outputs
wire [13:0] counter_out;
wire clk_div_by_12;
wire reset_sync;
reg en;
reg [8:0] encount;
// Instantiate the Unit Under Test (UUT)
internal_counter uut (
.clk(clk),
.counter_out(counter_out),
.reset(reset),
.clk_div_by_12(clk_div_by_12),
.reset_sync(reset_sync)
);
always begin
#6.25 clk = ~clk;

end


initial begin
// Initialize Inputs
clk = 0;
reset = 0;
en = 1'b1;
encount = 9'd0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

endmodule

제목 없음.png
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Moderator
Moderator
1,073 Views
Registered: ‎05-31-2017

Re: counter problem..

Hi @dlrmsqja1,

 

Thanks for sharing your TB file.

You have two different encount variables, one in TB and other in the UUT.

You were observing the encount value which is present in the TB so it was a constant as you have specified encount = 9'd0; in the TB.

To observe the encount value present in the UUT, please add the encount variable present in UUT and then restart the simulation, this time you will observe that the encount value present in the UUT has incremented as shown in the below snapshot

forum_count_tb_1.JPG

Observer dlrmsqja1
Observer
1,064 Views
Registered: ‎05-29-2017

Re: counter problem..

@shameera thank you! I can see incremented encount. But when I erase the  encount <= 9'd0; , counter_out is not increasing and of course encount is xxxxxxxx.   So I tried to make another always encount increment block like

 

always@(posedge clk) begin

encount = 9'd0;

  if (counter_out == 14'd210) begin

    encount = encount + 1;

end else begin

    encount = encount;

end

end

 

 

But it doesn't work....

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Moderator
Moderator
1,057 Views
Registered: ‎05-31-2017

Re: counter problem..

Hi @dlrmsqja1,

I think that you are trying to increment the encount value whenever counter_out value is 210. To obtain such operation, you have to modify your code to

initial
encount <= 9'd0;

always @(posedge clk) begin
counter_out <= 14'd0;

 

i.e., delete the encount <= 9'd0 statement in the always block and add it to the initial block. Then if you simulate and observe the value of encount in the uut then it would be as shown below

Capture_tb_2.JPG

Here I have attached the UUT file for your reference.

 

 

Observer dlrmsqja1
Observer
983 Views
Registered: ‎05-29-2017

Re: counter problem..

thanks! it was great help!

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