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Visitor irshs
Visitor
11,822 Views
Registered: ‎02-05-2015

custom IP works in simulation but not on hardware

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Hello,

 

I am currently starting with VHDL and I am also trying to get a working toolchain with Vivado. Therefore I try the following chain (with Vivado):

 

1. write simple entity in VHDL (also testbench) -----> 2. run behavioral simulation -----> 3. create IP core -----> 4. create a project (block design) to verify IP on hw

 

For hardware testing I use the Zed Board.

Currently I stuck at 4. (verify IP with hw). For a better understanding I describe the preceding steps:

 

1. The custom core shall get a LED blinking with 1Hz. The code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BlinkLED is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           led_out : out STD_LOGIC);
end BlinkLED;

architecture Behavioral of BlinkLED is

constant CLK_COUNT: integer := 50*10**6/4;        --500ms on at 50MHz

signal out_val: STD_LOGIC := '1';
signal clk_cnt: integer;

begin
    BLINK: process (clk, rst)
    begin
        if rst = '1' then
            clk_cnt <= CLK_COUNT;
            led_out <= '0';
        elsif clk = '1' and clk'event then
            if clk_cnt = 0 then
                led_out <= out_val;
                out_val <= not out_val;
                clk_cnt <= CLK_COUNT;
            else
                clk_cnt <= clk_cnt - 1;
            end if;
        end if;
    end process;

end Behavioral;

 

2. The simulated result looks as I expected it:

     The clockperiode (clk) of testbench is 20ns, the reset (rst) is pulled from initial '1' to '0' after 80ns:

Vivado_sim.png

 

3. With Tools -> Create and Pakage IP -> Next -> pakage current project -> include .xci files -> pakage IP I created the core.

 

4. In a new project I created following block design to test my core "BlinkLED_v1_0":

Vovado_block_design.png

- to verify that I am correctly accesing the LEDs (with constraints file) on the Zedboard I write a logic '1' to LED1. 

- to set the rst input of my BlinkLED core to '0' I invert the logic_1 signal with the utility_vector_logic.

- an output port (right click -> make external) of the BlinkLED core is made and connected (contstraints file) to LED0

 

Creating the bitfile works without critical warnings. When I program the FPGA with the bitfile I receive following output:

- LED1 turns on (as expected)

- LED0 does not turn on nor is blinking (not as expected).

 

What could be the reason for the this difference in simulation and in real hw?

 

Greetings

 

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Visitor irshs
Visitor
20,243 Views
Registered: ‎02-05-2015

Re: custom IP works in simulation but not on hardware

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Hello comunity,

 

I guess I figured out the problem. It seems that the VHDL code was correct...

 

It is due to the clock. I tried to put the clock on an output pin to measure it with the oscilloskope. But there was no clock. So I guess the processings system 7 core doesn´t start by default (I guess some comands are necessary in SDK similar to post: http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/PL-Clocks-on-Zynq-ZC706/td-p/306483). So no clock is working for the PL.

 

At the Zynq (Zed Board) on pin Y9 there is an independent clock for the FPGA. It works without starting the ARM cores. If I create an input port for the clock and connect it to the BlinkLED core (see image) it works (without the processing system 7 core).

Vivado_block_clk_in.png

 

I guess the design from my first post works aswell, when its started from SDK...

 

 

View solution in original post

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5 Replies
Scholar austin
Scholar
11,815 Views
Registered: ‎02-27-2008

Re: custom IP works in simulation but not on hardware

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i,

 

Either your reset is not what you think it is in the actual hardware, or the clock is not there, or the constant you have chosen isn't anywhere near the blink rate you think it is.

 

I suspect the latter, as an integer is defined by you for its range:

 

type type_name is range integer_range ;

 

So, how does the value stated get computed?  What size is the integer (default)?

 

Simulating VHDL is not the same as synthesis, placement, and routing of the VHDL.  It is a required first step in any design (if the simulation does not work then there is no hope the hardware will work).  But a successful simulation does not say the hardware will work (as you see).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor irshs
Visitor
11,797 Views
Registered: ‎02-05-2015

Re: custom IP works in simulation but not on hardware

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Hi,

thanks for the reply.

 

My first idea was aswell that maybe the reset gives me that error. Therefore I testet it with the remaining LEDs at my Zed Board. When I put a logic '1' at the output pins for the LEDs than they are flashing. If I invert the logic '1' with the utility_vector_logic than they are not flashing. Therefore I guess the error must be due to something else.

 

I set the PL clock (FCLK_CLK0) in Vivado via right click on Zynq Processing System --> customize block --> clock configuration on 50MHz. Than I connected it to the BlinkLED core. Can it be somehow possible that the clock isn´t there? I could check it with an oszilloscope when I route the clock to an output pin.

 

That the constant has a wrong value (not near the blink rate) I thought I excluded by the simulation. There I got the wanted behaviour at the output of the BlinkLED core. Sorry I am not sure what you mean with: " how does the value stated get computed"? I used the code as posted above for package it with Vivado. I just defined the constant as an integer, so I guess the length must be the default value. I will try to enlarge the integer length and post the results.

 

I forgot to post the constraints I used for the (not working) example above:

#  LED0
set_property iostandard "LVCMOS25" [get_ports "led_out"]
set_property PACKAGE_PIN "T22" [get_ports "led_out"]

#  LED1
set_property iostandard "LVCMOS25" [get_ports "logic_1"]
set_property PACKAGE_PIN "T21" [get_ports "logic_1"]

 

What else could I try to figure out the error in my design? Sorry for that questioning. I know its a simple design but I am new to this toolchain and VHDL. So I have to keep it simple (anyway I don´t get it running) ;-) 

 

Greetings

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Visitor irshs
Visitor
11,787 Views
Registered: ‎02-05-2015

Re: custom IP works in simulation but not on hardware

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Ok now I checked the integer value of my clk_cnt. I replaced :

signal clk_cnt: integer;

with:

signal clk_cnt: integer range 0 to (CLK_COUNT+1);

in my VHDL code. When I understood the definition correctly than the integer type fits the size of the signal  to the defined range. But the result is still the same. The LED0 doesn´t blink at all. Do you have some more ideas how I could debug it to find the error? I even checked if the LED is broken :-)

 

 

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Scholar austin
Scholar
11,778 Views
Registered: ‎02-27-2008

Re: custom IP works in simulation but not on hardware

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Try a 32 bit value,

 

Set it explicitely:  0xffff ffff h, (or the value you wish -- do not rely on computing it the way you have done which may be fine if you program in c, but I do not think works in VHDL....)

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor irshs
Visitor
20,244 Views
Registered: ‎02-05-2015

Re: custom IP works in simulation but not on hardware

Jump to solution

Hello comunity,

 

I guess I figured out the problem. It seems that the VHDL code was correct...

 

It is due to the clock. I tried to put the clock on an output pin to measure it with the oscilloskope. But there was no clock. So I guess the processings system 7 core doesn´t start by default (I guess some comands are necessary in SDK similar to post: http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/PL-Clocks-on-Zynq-ZC706/td-p/306483). So no clock is working for the PL.

 

At the Zynq (Zed Board) on pin Y9 there is an independent clock for the FPGA. It works without starting the ARM cores. If I create an input port for the clock and connect it to the BlinkLED core (see image) it works (without the processing system 7 core).

Vivado_block_clk_in.png

 

I guess the design from my first post works aswell, when its started from SDK...

 

 

View solution in original post

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