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Registered: ‎10-16-2019

data in uart is not getting received

The data is getting shifted in uart but it is not being received in RDR. i think the problem is fsm state 2 which is unable to generate the respective control signals shiftRSR and load_RDR and counter1 is being reset so its going back to idle state very soon. Please tell where it is going wrong. The verilog code attachment is below.

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