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Newbie
Newbie
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Registered: ‎05-29-2020

design of FIR filter

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i am designing FIR Low pass filter of cutoff frequency 120 Hz,with 100 taps and data width is 32bit.i am can i use '*' operator for multiplications as per FIR Structure or i have to design  special multiplier block for multiplication.

i had used '*' operator for multiplication,in behavioral simulation i got very good results, is it okay to synthesize the design and implement it ?.

 

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: design of FIR filter

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@mahi,

You haven't mentioned  the sample rate you want to operate at.  The sample rate will determine the algorithm you implement.  For example, if your sample rate is the system clock rate (50MHz or higher in general, but not specifically) then you might want to use an algorithm like this one.  It will use one DSP multiply per coefficient.  If the filter is symmetric (most FIR's are), you can drop that in half by applying the symmetry first.  If on the other hand your sample rate is much slower than the system clock rate, then you can reuse multiplies and so get by with perhaps only using one multiply per clock cycle.  You can also play the symmetric trick and use half as many multiplies, as discussed here.

Those would describe straightforward implementations.

Most FIR implementations for really low bandwidth but operating on high sample rate signals use multirate approaches, such as Fred Harris discusses in his text on the topic.  You'd then process the signal in stages.  The first stage would downsample the signal using some form of CIC filter.  No multiplies required.  The second stage would then apply something like the slow filter above.  This is required because 1) CIC filters are sloppy, and don't have a very flat passband, and so 2) you have at least one (if not two) more decimations required.

Another solution you might wish to consider uses the multirate techniques above, but then also resamples the signal when done back up to the system clock rate.  This solution is one I've wanted to build often enough, but not (yet) had the chance to play with.  Still, it's basic textbook stuff.

Dan

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: design of FIR filter

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@mahi,

Yes you can use the * operator. The synthesis tool will infer mult blocks.

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Newbie
Newbie
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Registered: ‎05-29-2020

Re: design of FIR filter

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okay,in my design there will be 100 multiplier blocks with two inputs of 32 bit and output of 64 bit.is there any error while synthesis and implementation ?.

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Voyager
Voyager
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Registered: ‎06-20-2012

Re: design of FIR filter

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@mahi 

Code with '*' and compile.

The largest FPGAs have thousands multipliers.

== If this was helpful, please feel free to give Kudos, and close if it answers your question ==
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Registered: ‎06-21-2017

Re: design of FIR filter

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Be sure to code in a couple pipeline registers if you want to run at a fairly high clock frequency.  64 bits out probably means two DSP cells per multiply.  You will need a few register delays to make this work.

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: design of FIR filter

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@mahi,

You haven't mentioned  the sample rate you want to operate at.  The sample rate will determine the algorithm you implement.  For example, if your sample rate is the system clock rate (50MHz or higher in general, but not specifically) then you might want to use an algorithm like this one.  It will use one DSP multiply per coefficient.  If the filter is symmetric (most FIR's are), you can drop that in half by applying the symmetry first.  If on the other hand your sample rate is much slower than the system clock rate, then you can reuse multiplies and so get by with perhaps only using one multiply per clock cycle.  You can also play the symmetric trick and use half as many multiplies, as discussed here.

Those would describe straightforward implementations.

Most FIR implementations for really low bandwidth but operating on high sample rate signals use multirate approaches, such as Fred Harris discusses in his text on the topic.  You'd then process the signal in stages.  The first stage would downsample the signal using some form of CIC filter.  No multiplies required.  The second stage would then apply something like the slow filter above.  This is required because 1) CIC filters are sloppy, and don't have a very flat passband, and so 2) you have at least one (if not two) more decimations required.

Another solution you might wish to consider uses the multirate techniques above, but then also resamples the signal when done back up to the system clock rate.  This solution is one I've wanted to build often enough, but not (yet) had the chance to play with.  Still, it's basic textbook stuff.

Dan

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