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Scholar ronnywebers
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Registered: ‎10-10-2014

difference between orange and red signals in a simulation wcfg file

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I'm wondering what the exact difference is when a signal is coloured orange vs red in a simulation result.

 

in the screenshot below you can observe that :

 

* running_average[15:0] is orange until the first rising clock edge, then it turns red. A bit later when the reset signal becomes active, it turns green.

* Some other signals just start off red from the very beginning of the simulation

 

so when is a signal coloured orange vs red?

 

orange red.png

 

 

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Moderator
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Registered: ‎11-09-2015

Re: difference between orange and red signals in a simulation wcfg file

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Hi @ronnywebers,

 

U (in orange), means unitialized. It just means that you didn't assign a value to the signals. In HW you will have the reset value or a random value

 

X (in red) stands for Forcing Unknown. There is several reason to have this on simulation:

-> operation on unitialized signals

-> Sometimes it is used to indicate a corruption (ex BRAM simulation) or an error in the core (simulation behavior described in the simulation model)

 

Usually I don't care about the U values (orange) but I am carreful about X values (could be errors, not always).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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6,546 Views
Registered: ‎11-09-2015

Re: difference between orange and red signals in a simulation wcfg file

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Hi @ronnywebers,

 

U (in orange), means unitialized. It just means that you didn't assign a value to the signals. In HW you will have the reset value or a random value

 

X (in red) stands for Forcing Unknown. There is several reason to have this on simulation:

-> operation on unitialized signals

-> Sometimes it is used to indicate a corruption (ex BRAM simulation) or an error in the core (simulation behavior described in the simulation model)

 

Usually I don't care about the U values (orange) but I am carreful about X values (could be errors, not always).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: difference between orange and red signals in a simulation wcfg file

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@florentw, I came across a case of such a 'red' signal that looks harmless (I think) :

 

red sim.png

 

 

 

...
    signal conf_bit_cntr   : unsigned(5 downto 0); 
    signal s_max_count_tmp : unsigned(5 downto 0);

begin    
...

    process(clock)
    begin
        if rising_edge(clock) then
            if (conf_bit_cntr > 16) then
                s_max_count_tmp <= (others => '0');
            else
                s_max_count_tmp <= conf_bit_cntr - 1;  <--- this causes the 'red' signal (?)
            end if;
        end if;
    end process;

    -- non-clocked, such that max_count is valid when done = '1'
    max_count <= std_logic_vector(s_max_count_tmp(3 downto 0));

 

so I think that the (short) red signal comes from the 'minus 1' operation on conf_bit_cntr which is at the very first rising edge 'U' (initialised), is that correct? And on the next rising edge, propagation makes that it turns green again.

 

Q : I can easily get rid of the red signal by initialising the signals :

 

    signal conf_bit_cntr   : unsigned(5 downto 0) := (others => '0'); 
    signal s_max_count_tmp : unsigned(5 downto 0) := (others => '0');

but I don't see it often in other code / books / examples ... or at least not consistent, some signals get an initial value, others not. 

 

What is recommended / good practice? Give each signal an initial value?

 

I've been thinking that it might be interesting to do this initialisation only in cases where the simulation gives red signals, so you can see that your code 'resolves' from signals with an uninitialised  state (?)

 

 

 

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Moderator
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Registered: ‎11-09-2015

Re: difference between orange and red signals in a simulation wcfg file

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Hi @ronnywebers,

 

so I think that the (short) red signal comes from the 'minus 1' operation on conf_bit_cntr which is at the very first rising edge 'U' (initialised), is that correct?

-> Yes in this case the red signals is because you are doing operation on a initialized values.

 

What is recommended / good practice? Give each signal an initial value?

-> I am not sure if there is really a recommended practice for this. If you know that you won't use the data at the time where it is in red, then there is no need to initialize it, except if you want a nicer simulation result. In the same time, it does not hurt to have a initial value for each signals. Xilinx devices have a dedicated global set/reset signal (GSR). This signal sets the initial value of all sequential cells in hardware at the end of device configuration. So you won't use more resources by giving initial values.

Most of the primitives have a default values of zero by default. So if even if you set the value to 0 in the code, you won't see the difference in HW (only in simulation).

 

What is recommended however is to remove resets as much as possible and to replace them with initials values.

 

Hope that is clear,

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: difference between orange and red signals in a simulation wcfg file

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@florentw side question : if I would stop using std_logic and std_logic_vector, and use only bit and bit_vector, wouldn't this make life simpeler? Like there are only 2 states a bit can get : 0 and 1, no uninitialised state etc. That would be closer to real hardware, not?

 

Of course if I need 'Z' then I cannot but use std_logic. But for the most part I don't need 'Z' ... 

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