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Visitor
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Registered: ‎02-12-2020

## don't care condition at the if statement

I want to make a priority encoder.

Firstly, I write a code as follows.

module pri_enc8(a,y,v);
input a;
output y,v;

wire [7:0] a;
wire [2:0] y;
wire v;

assign { y[2:0] , v } = (a == 8'b0000_0000) ? 4'bxxx0 :
(a == 8'b1xxx_xxxx) ? 4'b1111 :
(a == 8'b01xx_xxxx)? 4'b1101 :
(a == 8'b001x_xxxx) ? 4'b1011 :
(a == 8'b0001_xxxx) ? 4'b1101 :
(a == 8'b0000_1xxx) ? 4'b0111 :
(a == 8'b0000_01xx) ? 4'b0101 :
(a == 8'b0000_001x) ? 4'b0011 : 4'b0001 ;

endmodule

but this code makes the output contain don't care in any cases not showing 1.

So I change the code as follows

module pri_enc8(a,y,v);
input a;
output y,v;

wire [7:0] a;
wire [2:0] y;
wire v;

assign { y[2:0] , v } = (a[7] == 1 ) ? 4'b1111 :
(a[6] == 1 ) ? 4'b1101 :
(a[5] == 1 ) ? 4'b1011 :
(a[4] == 1) ? 4'b1101 :
(a[3] == 1) ? 4'b0111 :
(a[2] == 1) ? 4'b0101 :
(a[1] == 1) ? 4'b0011 :
(a[0] == 1) ? 4'b0001 : 4'bxxx0;

endmodule

And finally it shows the output as I want.

Is there any problem on my first code?

More specifically saying, is there any problem using don't care at the conditional part?

Thanks.

1 Solution

Accepted Solutions
Highlighted
Guide
337 Views
Registered: ‎01-23-2009

## Re: don't care condition at the if statement

Use the casex statement

```always @(*) begin
casex (a)
8'b1???_????: {y[2:0],v} = 4'b1111;
8'd01??_????: {y[2:0],v} = 4'b1101;
---
endcase
end```
4 Replies
Highlighted
Guide
338 Views
Registered: ‎01-23-2009

## Re: don't care condition at the if statement

Use the casex statement

```always @(*) begin
casex (a)
8'b1???_????: {y[2:0],v} = 4'b1111;
8'd01??_????: {y[2:0],v} = 4'b1101;
---
endcase
end```
Highlighted
Visitor
321 Views
Registered: ‎02-12-2020

## Re: don't care condition at the if statement

Thanks bro. It works seamlessly.
But I want to know why the first code of mine doesn't work and why your code works.
Can you tell me the reason?
Guide
302 Views
Registered: ‎01-23-2009

## Re: don't care condition at the if statement

But I want to know why the first code of mine doesn't work and why your code works.

Basically because you have a misunderstanding of what 'x' means. The 'x' doesn't mean "don't care" it means "don't know". So when you have an operation with an operand with X's in it, the rules for how it treats X depends on the operation, but in the case of comparisons (== != < > <= >=) it is pretty simple - if any bit of either operand has an X in it, then the result of the comparison is an X - "I don't know if the two operands are equal, at least one has a bit that is unknown". So all your comparisons resolve to X.

The next question is "what happens in a ternery operator when the selector is X" - the answer is pretty complicated, but needless to say, this doesn't accomplish what you are trying to do.

The only place an X represents a "don't care" according to the Verilog language is in the selector of a casex statement (the casex treats X, Z, and ? as "don't care", the casez only treats Z and ? as "don't care") - this is what I used in my code.

Finally, and this is not part of the language, most synthesis tools will interpret an assignment to X as a don't care; if you are assigning a reg/wire to X, by definition the value is unknown. Since it is unknown, it could be a 0, or it could be a 1 - the synthesis tool has to choose one or the other, so it chooses "whichever is simpler for the logic". So, effectively, the synthesis tools treat assignment to X as a "don't care".

Avrum

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Visitor
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Registered: ‎02-12-2020