cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Voyager
Voyager
1,336 Views
Registered: ‎06-26-2015

dual port bram issue

Jump to solution

Update: run a sim, dual port ram show the same behavior in BRAM_controller mode see post 2

 

I create a dual port BRAM, with porta-> axi_bram_controller.  portb-> FPGA core.

but for some reason, it only read the data on last address I wrote too, no matter what address I change on porta or portb.

I look at chipscope, the ram output doesn't change when addr change

 

the 1st screen show last byte write to addr 1, and it seem working but then even addr=0 for porta/portb, its shows value write to addrs 1.

2nd screen is software write read from ram

 

3rd screen shows read from addr0 or 1 don't change output.

 

4th screen show data write correctly from software to porta addr=0

 

so I'm expecting at addrs 0 its 0 to 1f, but its not.

 

my portb_en =1 all the time.

 

ram.jpg

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Voyager
Voyager
1,807 Views
Registered: ‎06-26-2015
forgot the 32bit address is byte align so the lower 5 bits address is ignored

View solution in original post

0 Kudos
2 Replies
Highlighted
Voyager
Voyager
1,311 Views
Registered: ‎06-26-2015

so I run a simulation dual port ram in BRAM Controller mode

I'm getting same result.  not matter what address I change(port a/port b), the data is stuck at last address I wrote.

wrote 000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f  at addr 0 on porta

wrote 202122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f  at addr 1 on porta

 

enable both porta_en/portb_en, all address set to 0, write_byte = all 0, yet the dout shows the value from address 1.

 

ram2.jpg

 

0 Kudos
Highlighted
Voyager
Voyager
1,808 Views
Registered: ‎06-26-2015
forgot the 32bit address is byte align so the lower 5 bits address is ignored

View solution in original post

0 Kudos