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Newbie
Newbie
250 Views
Registered: ‎07-27-2020

error in System Verilog

why I am getting this error. The "System Verilog Cover group" is not supported yet for simulation. I am using 2016.4 version

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

Please use the latest Vivado version, 2016.4 is too old, which may not support covergroup.

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Moderator
Moderator
31 Views
Registered: ‎09-15-2016

Hi @sudheer397 ,

Please try using Vivado 2019.x or later versions of Vivado.

Thanks & Regards,
Sravanthi B
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