07-27-2020 06:17 AM
why I am getting this error. The "System Verilog Cover group" is not supported yet for simulation. I am using 2016.4 version
07-27-2020 08:11 PM
Please use the latest Vivado version, 2016.4 is too old, which may not support covergroup.
10-15-2020 04:27 AM
Hi @sudheer397 ,
Please try using Vivado 2019.x or later versions of Vivado.