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juloau
Visitor
Visitor
797 Views
Registered: ‎01-29-2021

error

It appears to me when I try to compilate the program also, in the simulation there are red lines in the graph.

INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

I would appreciate an answer.

As soon as possible, please.

 

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9 Replies
drjohnsmith
Teacher
Teacher
782 Views
Registered: ‎07-09-2009

From that description it could be just about anything

 

Suggest you give a lot more detail

Start with what OS and what tool your using, and how you are starting the tool , from a TCL script or a gui click ?

 

include snapshot of the "red line" problem

  include as much detail about what you were doing and expecting to happen at the time.

also include, have yo had this setup working , or is this a new setup 

 

Just a guess,

   you don't by some chance have ISE on W10 ?

  if so , did you install the correct version of ISE with the Oracal Virtual machine

 

 

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miti
Xilinx Employee
Xilinx Employee
683 Views
Registered: ‎06-10-2020

Hi @juloau ,

Can you please upload the project and details like on which OS / which version you are using.

This is help to reproduce the issue at our end.

juloau
Visitor
Visitor
676 Views
Registered: ‎01-29-2021

Hopefully I could fix that error but, others appeared. 

I´m making an electronic piano using a codifier and a mux. I checked its syntax  and behaviour  which are ok but, the simulation does not respond and in "Implement Desing" appear thes errors:

WARNING:Security:42 - Your software subscription period has lapsed. Your current
WARNING:LIT:701 - PAD symbol "BTN<3>" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "BTN<3>" is not constrained (LOC) to a specific
location.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

How can I fix them?

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juloau
Visitor
Visitor
667 Views
Registered: ‎01-29-2021

I´m upploading  the code:

----------------------------------------------------------------------------------
-- Company:
-- Engineer: Julia López Augusto
--
-- Create Date: 16:32:47 01/27/2021
-- Design Name:
-- Module Name: PIANO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PIANO is
port(
BTN: in STD_LOGIC_VECTOR(3 downto 1);
Zout: out STD_LOGIC;
SNL: in STD_LOGIC
);
end PIANO;


architecture Behavioral of PIANO is

SIGNAL S: STD_LOGIC_VECTOR(1 downto 0);
SIGNAL SON: STD_LOGIC_VECTOR(3 downto 1);

begin
COD: process (BTN)
begin
if (BTN(3)= '1') then
S<="11";
elsif (BTN(2)= '1') then
S<="10";
elsif (BTN(1)= '1') then
S<="01";
else
S<="00";
end if;

end process;

MUX: process (S, SON, SNL)
begin
SON(3) <= S(1);
SON(2) <= S(0);
SON(1) <= SNL;

if (S(1) ='0' and S(0) = '0') then
Zout <= '0';
elsif (S(1) ='0' and S(0) = '1') then
Zout <= SON(1);
elsif (S(1) ='1' and S(0) = '0') then
Zout <= SON(2);
else
Zout <= SON(3);
end if;

end process;

end Behavioral;

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juloau
Visitor
Visitor
667 Views
Registered: ‎01-29-2021

I´m uploading the test bench:

--------------------------------------------------------------------------------
-- Company:
-- Engineer: Julia López Augusto
--
-- Create Date: 18:58:30 01/27/2021
-- Design Name:
-- Module Name: /opt/Xilinx/PRACTICAS/PIANO/PIANO_tb.vhd
-- Project Name: PIANO
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PIANO
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY PIANO_tb IS
END PIANO_tb;

ARCHITECTURE behavior OF PIANO_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT PIANO
PORT(
BTN : IN std_logic_vector(3 downto 1);
Zout : OUT std_logic;
S: STD_LOGIC_VECTOR(1 downto 0);
SON: IN STD_LOGIC_VECTOR(3 downto 1)


);
END COMPONENT;

--Inputs
signal BTN1 : std_logic_vector(3 downto 1) := "000";
-- signal S: STD_LOGIC_VECTOR(1 downto 0);
signal SON1: STD_LOGIC;

--Outputs
signal Zout1 : std_logic;
signal S1: STD_LOGIC_VECTOR(1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: PIANO PORT MAP (
BTN => BTN1,
S => S1,
SON(3) => S1(1),
SON(2) => S1(0),
SON(1) => SON1,
Zout => Zout1
);

-- Stimulus process
Process_BTN1: process
begin

BTN1<= "000";
wait for 200 ns;

BTN1<= "001";
wait for 200 ns;

BTN1<= "010";
wait for 200 ns;

BTN1<= "100";
wait for 200 ns;

BTN1<= "011";
wait for 200 ns;

BTN1<= "110";
wait for 200 ns;

BTN1<= "111";
wait for 200 ns;

end process;

Process_S1: process
begin

S1<= "00";
wait for 200 ns;

S1<= "01";
wait for 200 ns;

S1<= "10";
wait for 200 ns;

S1<= "11";
wait for 200 ns;

end process;

Process_S1_0: process
begin
--s1(0) ES IGUAL A SON3

S1(0)<= '1';
wait for 10 ns;

S1(0)<= '0';
wait for 30 ns;

end process;

Process_S1_1: process
begin
--s1(1) ES IGUAL A SON 2

S1(1)<= '1';
wait for 40 ns;

S1(1)<= '0';
wait for 40 ns;

end process;

Process_SON1: process
begin

SON1<= '1';
wait for 60 ns;

SON1<= '0';
wait for 60 ns;

end process;

END;

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juloau
Visitor
Visitor
661 Views
Registered: ‎01-29-2021

I have to say that I´m a beginner in programmming VHDL and I was asked to represent in VHDL the diagram I am attaching. So, could you tell me  if what I´ve done it´s ok? 

I´ll be very glad.

Thanks in advance.

 

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drjohnsmith
Teacher
Teacher
607 Views
Registered: ‎07-09-2009

process( BTN, SON, TERRA )

begin

CASE ( BT ) is

when B"11" =>

    Zout <= SON(3);

when B"10" =>

    Zout <= SON(2);

when B"01" =>

    Zout <= SON(1);

when others =>

  Zout <= TERRA;

end case;

end process;

 

 

 

 

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juloau
Visitor
Visitor
596 Views
Registered: ‎01-29-2021

I really appreciate what you´ve done but I have to handle it with 2 processes(one with  a mux and the other with the codifier)  and using if then else clauses

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juloau
Visitor
Visitor
485 Views
Registered: ‎01-29-2021

Please, I need it for an important proyect

 

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