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Registered: ‎01-15-2019

export_simulation -> how to export the whole RTL (BlockDesign+PL+PS)

Hi All,

I need to export the WHOLE design (BlockDesign+RTL) from my Vivado Project to Full Chip Simulation.

Does the export_simulation command work for the whole design or just for IPs?

When I do 'File -> Export -> Export Simulation', the following TCL command is generated:

export_simulation  -lib_map_path "C:/Projects/xgs/exp2sim" -export_source_files -force -directory "C:/Users/USER/AppData/Roaming/Xilinx/Vivado/." -simulator questa  
-ip_user_files_dir "C:/Projects/xgs/Zynq7_Vivado/xgs.ip_user_files" 
-ipstatic_source_dir "C:/Projects/xgs/Zynq7_Vivado/xgs.ip_user_files/ipstatic" -use_ip_compiled_libs

But, the exported files include just IPs, which are instantiated in the Block Design (system wrapper). The design files, which are out of the Block Design scope, were not exported... Should it be so?

How to export the ALL design files in order to send them to the Verification team?

Thank you!


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Xilinx Employee
Xilinx Employee
Registered: ‎07-16-2008

回复: export_simulation -> how to export the whole RTL (BlockDesign+PL+PS)

The way you ran export_simulation should generate the script for the active simulation top.

Is the BD as well as other design files under the hierarchy of simulation test bench top?

Don't forget to reply, kudo, and accept as solution.
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