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Visitor 6012
Visitor
5,893 Views
Registered: ‎09-21-2016

file needs to be re-saved since std.standard changed

Using Vivado 2016.2 generates the following error when file type specified as VHDL 2008 and VHDL code contains a conditional signal assignment within a process (allowed in VHDL 2008).

...
  zero <= '1' when (unsigned(result_v(15 downto 0)) = 0) else '0';  -- VHDL 2008
end process ALU;

ERROR: [VRFC 10-113] C:/proj/my_prj/my_prj.sim/sim_1/behav/xsim.dir/xil_defaultlib/defs_pkg.vdb needs to be re-saved since std.standard changed
ERROR: [VRFC 10-147] xil_defaultlib.defs_pkg failed to restore

 

The error is referencing a user created package that is imported into the design file that is using VHDL 2008 syntax.  The package uses non-VHDL 2008 syntax.


Have to move conditional signal assignment outside of process (pre-VHDL 2008 syntax) and set file type to VHDL for successful compilation.

Also note, pre-VHDL 2008 syntax and setting file type to VHDL 2008 generates same error as above.  So, appears that setting file type to VHDL 2008 in general is throwing the above VRFC 10-113 error.

Please advise on fix / workaround.

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5 Replies
Xilinx Employee
Xilinx Employee
5,779 Views
Registered: ‎09-13-2014

Re: file needs to be re-saved since std.standard changed

Yes, this was a known issue which has been fixed in 2016.3. For the time being, you can set file type for all VHDL file as vhdl-2008 and with that, it should work in Vivado Simulator.

 

Let us know if you are still seeing any issue after above modification.

 

--dhiRAj

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Adventurer
Adventurer
3,802 Views
Registered: ‎06-09-2016

Re: file needs to be re-saved since std.standard changed

just for clarify because I have seen the same answer in another posts.

 

I´m using vivado 2017.1 and this error still apears!.

 

I tried to change all vhd files to vhdl 2008 but there is still some files inside block design I'm not able to modify.

 

What can I do?.

 

thanks.

 

 

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Visitor lsav
Visitor
942 Views
Registered: ‎09-30-2018

Re: file needs to be re-saved since std.standard changed

I have also just encountered the same problem in Vivado 2018.3!

 

I have a package which generates some global types and they are unconstrained thus requiring a 2008 file type syntax.

 

Stuck inbetween a rock and a hardplace!

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610 Views
Registered: ‎05-03-2012

Re: file needs to be re-saved since std.standard changed

I seem to get this error whenever i "touch" the constants package in my design.  It makes simulation impossible.

Invariably, modifying file properties to VHDL 2008 seems to fix things.  THis time, I had to change the test bench file properties and I'm back in business.  Deleting sim directories doesn't seem to work for me.

Kudos to all for ideas fixing these sometimes cryptic errors.

Vivado 2018.2

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Scholar richardhead
Scholar
590 Views
Registered: ‎08-01-2012

Re: file needs to be re-saved since std.standard changed

@cliffordjb123 

Are all source VHD files set to 2008? Just wondering how well Xilinx copes with cross version compliance. Eg. using a 2008 package in a '93 file may be ok if all you were using was constants, but it might cause some dependencies in the compiler that might cause errors (which probably shouldnt).

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