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moon5756
Explorer
Explorer
1,250 Views
Registered: ‎09-05-2015

first element not shown in fifo simulation

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screenshot.JPG

As shown on the figure above, first din=5 is not shown in dout. I tried increasing clk delay but didn't work.

One thing to note is that rd_en is combinational gated output of start_read so that no matter how long start_read is asserted, rd_en is asserted for one clock cycle.

 

Thanks in advance.

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moon5756
Explorer
Explorer
1,627 Views
Registered: ‎09-05-2015

Never mind, resolved by asserting reset for at least 5 clock cycles! Thanks!

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moon5756
Explorer
Explorer
1,628 Views
Registered: ‎09-05-2015

Never mind, resolved by asserting reset for at least 5 clock cycles! Thanks!

View solution in original post

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bandi
Moderator
Moderator
1,129 Views
Registered: ‎09-15-2016

Hi @moon5756,

 

I am glad to know that the issue got resolved. Can you please close this thread by marking your post as accepted solution.

 

Thanks & Regards,

Sravanthi B

 

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