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assaad1-

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05-06-2019 09:38 AM

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Registered:
10-16-2018

fixed point operation in VHDL unexpected result

Hello everyone i have a problem in my result and more precisely in the arithmetical operation. i have two text file contains 16 bit coded pixel. my operation is: (A + 0.14 (A-B) +0.0032 (A-B) * (A-B) +0.83) * 10

I use the package fixed point the operations gives a correct result as to A higher than B but in the opposite it gives different result which is great for example 0110111010110100 I do not know the problem.I downloaded files A and B and the result

14 Replies

bruce_karaffa

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05-06-2019 10:13 AM

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06-21-2017

Re: fixed point operation in VHDL unexpected result

We need to see the code to help.

drjohnsmith

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05-06-2019 10:25 AM

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07-09-2009

Re: fixed point operation in VHDL unexpected result

how are you expecting the vhdl to be implemented in the real chip ?

You also need to take into account all packages your using ,

and what you have declared the signals as.

this might be of use

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

assaad1-

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05-06-2019 10:45 AM

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10-16-2018

Re: fixed point operation in VHDL unexpected result

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

use work. fixed_pkg.all;

also im using mu unput as std_logic_vector the i convert my inpit to ufixed to do the arithmetical operation

this is my declaration of my the numbers:

signal i : integer;

signal j : integer;

signal k : integer;

constant h1 : ufixed(32 downto -16) := to_ufixed(0.14, 32, -16);

constant h2 : ufixed(32 downto -16) := to_ufixed(0.0032, 32, -16);

constant h3 : ufixed(32 downto -16) := to_ufixed(0.83, 32, -16);

constant h4 : ufixed(32 downto -16) := to_ufixed(0.1, 32, -16);

constant h5 : ufixed(32 downto -16) := to_ufixed(10, 32, -16);

assaad1-

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05-06-2019 07:20 PM

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10-16-2018

Re: fixed point operation in VHDL unexpected result

drjohnsmith

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05-06-2019 11:02 PM

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Registered:
07-09-2009

Re: fixed point operation in VHDL unexpected result

do you mind posting that with formating please

richardhead

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05-07-2019 01:58 AM

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08-01-2012

Re: fixed point operation in VHDL unexpected result

Have you considered that the result might go negative?

ufixed is "Unsigned Fixed", therefore negative results are not handled, 0 -N wraps around

You should be using sfixed type instead.

drjohnsmith

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05-07-2019 02:12 AM

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Registered:
07-09-2009

Re: fixed point operation in VHDL unexpected result

why are yo using

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL

I'd strongly suggest using just

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL

A bit of a diatribe on it her

basicaly, there have been competing 'standards' over the years fomr a few companies trying to force / pre empt the IEEE process.

If yo uuse libraries form the multiple camps, then you ar ein to a world of pain, as som eof the definitoins disagree with each other, and th eway VHDL works, the last declared one wins,

so if you have two programs with none standard libraries in them, and in the two programs the they are declare din different order, then your results can differ.....

It is possible to do , and there are a few c;ever cases I have seen over th eyears,

but

you have been warned, don't mix vendors libraries.

if there is a proper IEEE lib available, use it.

richardhead

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05-07-2019 02:54 AM

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08-01-2012

Re: fixed point operation in VHDL unexpected result

The only clash is with std_logic_arith and numeric_std. numeric_std plays perfectly fine with std_logic_unsignd as they work on different types (numeric_std = signed/unsigned, std_logic_unisnged= std_logic_vector). Yes std_logic_unsigned is non-standard, but it works with all vendors, afaik, as expected (and they all use the synopsys version of the library rather than their own).

If you are in VHDL 2008, I would recommend using numeric_std_unsigned instead. Its basically the VHDL standardised version of std_logic_unsigned.

drjohnsmith

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05-07-2019 03:41 AM

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07-09-2009

Re: fixed point operation in VHDL unexpected result

assaad1-

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05-07-2019 06:03 AM

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10-16-2018

Re: fixed point operation in VHDL unexpected result

bruce_karaffa

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05-08-2019 09:30 AM

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06-21-2017

Re: fixed point operation in VHDL unexpected result

assaad1-

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05-15-2019 04:13 AM

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10-16-2018

Re: fixed point operation in VHDL unexpected result

drjohnsmith

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05-15-2019 05:46 AM

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Registered:
07-09-2009

Re: fixed point operation in VHDL unexpected result

A.txt is all zero.

your equaiton

(A + 0.14 (A-B) +0.0032 (A-B) * (A-B) +0.83) * 10

so A-B will be negative.

as said above , you need to work in signed numbers,

drjohnsmith

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05-15-2019 05:47 AM

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Registered:
07-09-2009

Re: fixed point operation in VHDL unexpected result

Run a simulaotin, and look at the intermediate results ,