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Contributor
Contributor
577 Views
Registered: ‎02-16-2018

flip-flop output following the input

Hi,

I am using vivado version 2018.2 and i have written a code for which I am seeing different simulation result.

The simulation and code snapshots are attached below.

In the code plp_fdbk_n_i is a input and in simulation I am seeing dut_ack_sync_reg_n_0 flop is changing @clock edge when  plp_fdbk_n_i  is changed from basics what I know is it should go low at next clock edge. 

Is this valid behaviour ?

verilog_code.JPG
simulation_wavef.JPG
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6 Replies
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Teacher
Teacher
575 Views
Registered: ‎07-09-2009

A quick thought, ( sorry verilog is not my language of choice )

move the phase of the clock, say invert it in the test bench, so data changes on the falling edge of the clock,

see if data out then changes with the data in or the clock.

 

 

 

 

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Scholar
Scholar
553 Views
Registered: ‎08-01-2012

how are you generating plp_fdbk_n_i  ?

This looks like a classic example of using specific time offsets in the testbench rather than being synchronised to clock, and hence creating your DUT input just before the clock edge.

for example, the code below can generate the issue:

reg clk = 1'b0;
reg ip;

always #5  clk =  ! clk; 

initial begin
  ip = 1'b0;
  #5;
  ip = 1'b1;
end
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Contributor
Contributor
527 Views
Registered: ‎02-16-2018

Hi Richardhead,

Even if the input changes @rising edge of clock , it should be captured in the next posedge of clock. And output should be delayed by one clock. 

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Scholar
Scholar
520 Views
Registered: ‎08-01-2012

i@007 

Yes it should, and your code should do that.

You  didnt post the testbench code - my code was an example of what I suspected you have done to cause it to change on what looks like the same edge, but it actually isnt. The input is changing just before the clock and causing the apparent error.

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Teacher
Teacher
496 Views
Registered: ‎07-09-2009

So what have you tried so far ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
482 Views
Registered: ‎05-31-2017

Hi i@007 ,

As correctly indicated by @richardhead & @drjohnsmith it's completely dependent on how have modeled the testbench. Here I have attached the similar code which I have tried at my end, which has test bench too showing the correct behavior for your reference.

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