04-02-2019 12:14 AM
I am using vivado version 2018.2 and i have written a code for which I am seeing different simulation result.
The simulation and code snapshots are attached below.
In the code plp_fdbk_n_i is a input and in simulation I am seeing dut_ack_sync_reg_n_0 flop is changing @clock edge when plp_fdbk_n_i is changed from basics what I know is it should go low at next clock edge.
Is this valid behaviour ?
04-02-2019 12:23 AM - edited 04-02-2019 03:28 AM
A quick thought, ( sorry verilog is not my language of choice )
move the phase of the clock, say invert it in the test bench, so data changes on the falling edge of the clock,
see if data out then changes with the data in or the clock.
04-02-2019 01:36 AM - edited 04-02-2019 01:39 AM
how are you generating plp_fdbk_n_i ?
This looks like a classic example of using specific time offsets in the testbench rather than being synchronised to clock, and hence creating your DUT input just before the clock edge.
for example, the code below can generate the issue:
reg clk = 1'b0; reg ip; always #5 clk = ! clk; initial begin ip = 1'b0; #5; ip = 1'b1; end
04-03-2019 12:37 AM
Even if the input changes @rising edge of clock , it should be captured in the next posedge of clock. And output should be delayed by one clock.
04-03-2019 01:01 AM
Yes it should, and your code should do that.
You didnt post the testbench code - my code was an example of what I suspected you have done to cause it to change on what looks like the same edge, but it actually isnt. The input is changing just before the clock and causing the apparent error.
04-03-2019 08:28 PM