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antonkurka
Contributor
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Registered: ‎03-14-2008

for loop in ISE14.7 issue

Hello
I am working with ISE14.7. In  my  new project I have to  implemented a old modul they are running in ISE11.5, but in the ISE14.7 they don't run in the simulation (modelSim PE2019.1)
My new project is with Kintex7.
The sequencis is the follow :

AblaufNETx: PROCESS(clk)
 VARIABLE Instr :STD_LOGIC_VECTOR(47 DOWNTO 0):=X"000000000000";
------------------------------------------
BEGIN
IF rising_edge(clk) THEN
 IF (nrst = '0') THEN
    Instr := X"000000000000";
     FOR i IN 0 TO 64 LOOP
          pack(i) <= X"00"; --initialise pack pendend reset
      END LOOP;
      Pack(0) <= X"20"; --uIDest(LSB) := 20h
      Pack(28) <=x"00";--uiCmd LSB := 00009A00H = Download paket
      Pack(29) <=X"9A";--uiCmd MSB
 ELSE
........

etc
---------------------------
declaration  for pack :
TYPE t_pack IS ARRAY(0 TO 64) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL pack : t_pack;

 in the simulation is  the "pack" allways  {xx} {xx} {xx} ....

I have also try to initialise after reset (nrst) in the ELSE part, the result is the same

The same sequencis run wthout problems also unter ISE11.5  with Spartan 6  and simulation
with ModelSim6.5

How is the solution to work arround of this problem.
thank You for advance
Anton


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9 Replies
hgleamon1
Teacher
Teacher
798 Views
Registered: ‎11-14-2011

Are you doing pre- or post- synthesis simulation?

"XX" means (generally) contention, so there is something else trying to drive the pack signal. Where else in your design is this used?

Can you show your testbench code?

 

I don't believe this is a loop problem but you could try changing the code to remove the loop and initialise the pack signal like this:

if (nrst = '0') then
  instr := (others => '0');
  pack <= (0 => X"20", 29 => X"9A", others => X"00");
else
 ...
end if;

 

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"That which we must learn to do, we learn by doing." - Aristotle
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antonkurka
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Registered: ‎03-14-2008

Hi, thank You for the prompt replay.
this problem i have is in the behavioral simulation.
Yes I also not believe  the problem is a loop, because I have many loop in this
project and this run ok.
Perhaps is the using of the procedure for read the data from "pack"  ???
On the attachement You see all relevant part of  programm.
Best regards
Anton

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richardhead
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Registered: ‎08-01-2012

This is a very odd procedure - it looks like a process. Are you sure you copied/pasted correctly?

Please can you post the whole code?

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antonkurka
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Registered: ‎03-14-2008

In this file "ProblemPack.vhd" I have only copy a part of code they are relevant , this is not the code thay  can run.
The "PROCESS  AblaufNetx" is complett and also procedure "SndPack" using of data of "Pack".
PROCESS NETxCOM You see a small part with  call of "SndPack", the rest part has nothing to do with the data of Pack.
Whole Code is first to long and second has nothing to do with the data of "Pack".
The declaration of "Pack" is as follow:

TYPE t_pack IS ARRAY(0 TO 64) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL pack : t_pack;

I suppose that's why there's a problem with the signal Pack it does not
can be initialized like another signals at the declaration.???
It is strange that the same processes under
ISE11.5 / ModelSim6.5 ran without problems
With the ModelSim6.5/ISE11.5 itis was not nessesery by signal declaration to define a init value.
On the other hand, at the ModelSimPE2019/ISE14.7 init value by signal declaration  must be defined.

 

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hgleamon1
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Registered: ‎11-14-2011

Do you get any warnings in the simulator when you compile and load the design or run the simulation? 

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"That which we must learn to do, we learn by doing." - Aristotle
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richardhead
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Registered: ‎08-01-2012

@antonkurka 

Without the code, there is little more I can suggest.

There is nothing wrong with that signal declaration and it can be initialised like any other signal.

 

Please post the code.

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antonkurka
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Registered: ‎03-14-2008

Hi,
thank You, in the time between i have find a solution. Now it's run ok.

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hgleamon1
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Teacher
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Registered: ‎11-14-2011

Could you explain the solution for others? Otherwise this thread is just a dead end (in any case you should mark the thread solved).

Thanks.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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antonkurka
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Registered: ‎03-14-2008

The problem was not the loop, they are not assigned array at the declaration.
This was not a problem with ISE11.5/modelSim6.5 but with the change to
ISE14.7/modelSimPE  it is very important to assigned all signals at the declaration.
For example in my case :
TYPE t_pack IS ARRAY(0 TO 64) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL pack : t_pack :=(OTHERS => "00000000");

for a not assigned signals in the declaration is later impossible to access or initialise in the process.

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